R8A77850ANBGV Renesas Electronics America, R8A77850ANBGV Datasheet - Page 152

IC SUPERH MPU ROMLESS 436-BGA

R8A77850ANBGV

Manufacturer Part Number
R8A77850ANBGV
Description
IC SUPERH MPU ROMLESS 436-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet

Specifications of R8A77850ANBGV

Core Processor
SH-4A
Core Size
32-Bit
Speed
600MHz
Connectivity
Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
Peripherals
DMA, POR, WDT
Number Of I /o
108
Program Memory Type
ROMless
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
1 V ~ 1.2 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
436-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R8A77850ANBGV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
5. Exception Handling
5.6.3
(1)
• Source: NMI pin edge detection
• Transition address: VBR + H'00000600
• Transition operations:
(2)
• Source: The interrupt mask level bits setting in SR is smaller than the interrupt level of
• Transition address: VBR + H'00000600
• Transition operations:
Rev.1.00 Jan. 10, 2008 Page 120 of 1658
REJ09B0261-0100
NMI()
{
}
The PC and SR contents for the instruction immediately after this exception is accepted are
saved in SPC and SSR. The R15 contents at this time are saved in SGR.
Exception code H'1C0 is set in INTEVT. The BL, MD, and RB bits are set to 1 in SR, and a
branch is made to PC = VBR + H'0600. When the BL bit in SR is 0, this interrupt is not
masked by the interrupt mask bits in SR, and is accepted at the highest priority level. When the
BL bit in SR is 1, a software setting can specify whether this interrupt is to be masked or
accepted. When the INTMU bit in CPUOPM is 1 and the NMI interrupt is accessed, B'1111 is
set to IMASK bit in SR. For details, see section 10, Interrupt Controller (INTC).
interrupt request, and the BL bit in SR is 0 (accepted at instruction boundary).
The PC contents immediately after the instruction at which the interrupt is accepted are set in
SPC. The SR and R15 contents at the time of acceptance are set in SSR and SGR.
NMI (Nonmaskable Interrupt)
General Interrupt Request
SPC = PC;
SSR = SR;
SGR = R15;
INTEVT = H'0000 01C0;
SR.MD = 1;
SR.RB = 1;
SR.BL = 1;
If (cond) SR.IMASK = B'1111;
PC = VBR + H'0000 0600;
Interrupts

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