R8A77850ANBGV Renesas Electronics America, R8A77850ANBGV Datasheet - Page 679

• Manufacturer Part Number: R8A77850ANBGV
• Description: IC SUPERH MPU ROMLESS 436-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850ANBGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

(7)
The PCIC supports cache coherency function.
When the PCIC functions as a target device, cache coherency is guaranteed on the PCI bus for
accesses from a master device both in host mode and normal mode. When a cacheable area of this
LSI is accessed, PCICSCR0/1 and PCICSAR0/1 should be set.
The following shows the usage notes for this function.
• Up to two conditions can be set for the snoop address. These two conditions are logical ORed
• When this function is used, a flush/purge request is issued to the CPU before memory
• Do not use the prefetch function when using this function. (Do not set the PFE bit in PCICR to
• Do not use this function when the CPU is in the sleep state. If a cache hit occurs when the CPU
• When using this function, do not use debugging functions using an emulator. (Do not use this
for address comparison.
read/write is performed in an access by an address hit. It seriously reduces the PCI bus transfer
speed and CPU performance.
1.)
is in the sleep state, an error occurs on the SuperHyway bus and memory read/write is not
performed. Specify the SNPMD bit (snoop mode) in PCICSCR to 00 (to turn off the snoop
function) before the CPU enters the sleep mode. To keep the coherency before/after the CPU
enters the sleep state, execute cache purge before the sleep instruction is executed.
function when using an emulator).
Figure 13.16 Cache Flush/Purge Execution Flow from PCI Bus to SuperHyway Bus
Cache Coherency
Internal bus address
PCI bus address
Execute read/write
No hit
Compare
Set
Hit
Cache snoop address register
Cache snoop control register
Execute read/write
Cache flash/purge
Rev.1.00 Jan. 10, 2008 Page 647 of 1658
13. PCI Controller (PCIC)
REJ09B0261-0100