R8A77850ANBGV Renesas Electronics America, R8A77850ANBGV Datasheet - Page 1600

• Manufacturer Part Number: R8A77850ANBGV
• Description: IC SUPERH MPU ROMLESS 436-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850ANBGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

32. Electrical Characteristics
32.3.1
Table 32.6 Clock and Control Signal Timing
Rev.1.00 Jan. 10, 2008 Page 1568 of 1658
REJ09B0261-0100
Item
EXTAL clock
input frequency
EXTAL clock
input cycle time
EXTAL clock input low pulse width
EXTAL clock input high pulse width
EXTAL clock input rise time
EXTAL clock input fall time
CLKOUT clock output (with use of PLL1/PLL2) f
CLKOUT clock output cycle time
CLKOUT clock output low pulse width
CLKOUT clock output high pulse width
CLKOUT clock output rise time
CLKOUT clock output fall time
CLKOUT clock output low pulse width
CLKOUT clock output high pulse width
Power-on oscillation settling time
Power-on oscillation settling time/mode
(MODE14, MODE10, MODE9, MODE4 to
MODE0) settling time
MODE (MODE13 to MODE11, MODE8 to
MODE5) reset setup time
Clock and Control Signal Timing
Divider 1: × 1, PLL1: × 72,
PLL2 in operation*
Divider 1: × 1, PLL1: × 36,
PLL2 in operation*
Divider 1: × 1, PLL1: × 72,
PLL2 in operation*
Divider 1: × 1, PLL1: × 36,
PLL2 in operation*
4
6
4
6
Symbol
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
EX
EXcyc
EXL
EXH
EXr
EXf
OP
CKOcyc
CKOL1
CKOH1
CKOr
CKOf
CKOL2
CKOH2
OSC1
OSCMD
MDRS
Min.
12
23
59
29
3.5
3.5
⎯
⎯
25
10
1
1
⎯
⎯
3
3
10
10
3
Max.
17
34
83
43
⎯
⎯
4
4
101
1000
⎯
⎯
3
3
⎯
⎯
⎯
⎯
⎯
Unit
MHz
ns
ns
ns
ns
ns
MHz
ns
ns
ns
ns
ns
ns
ns
ms
ms
t
cyc
Figure
32.1
32.1
32.1
32.1
32.1
32.2
32.2
32.2
32.2
32.2
32.3
32.3
32.4
32.4
32.6