R8A77850ANBGV Renesas Electronics America, R8A77850ANBGV Datasheet - Page 1481

• Manufacturer Part Number: R8A77850ANBGV
• Description: IC SUPERH MPU ROMLESS 436-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850ANBGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

28.3
Setting procedure examples are described below.
28.3.1
To output the data of port data registers (PADR to PRDR) from the GPIO output port, write B'01
to the corresponding two bits in port control registers (PACR to PRCR).
In this case, for each output port, the settings of the port pull-up control registers (PEPUPR,
PHPUPR, PJPUPR, PKPUPR, PLPUPR, PMPUPR, and PNPUPR), peripheral module select
register 1 (P1MSELR), peripheral module select register 2 (P2MSELR), and bus mode pin
(MODE11 and MODE12) are invalid.
Figure 28.1 shows an example of operation timing diagram when port A is used as an output port.
The output data is written to port data registers (PADR to PRDR) and then the data is output via
the corresponding port pins after one peripheral clock (Pck).
Usage Example
Port Output Function
CLKOUT
Peripheral clock (Pck)
Port A data register
PA7 to PA0
(D63/AD31 to D56/AD24)
Figure 28.1 Port A Data Output Timing Diagram
Data
Rev.1.00 Jan. 10, 2008 Page 1449 of 1658
Data
28. General Purpose I/O Ports (GPIO)
REJ09B0261-0100