R8A77850ANBGV Renesas Electronics America, R8A77850ANBGV Datasheet - Page 354

• Manufacturer Part Number: R8A77850ANBGV
• Description: IC SUPERH MPU ROMLESS 436-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850ANBGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

10. Interrupt Controller (INTC)
10.3.5
INT2GPIC enables interrupt requests input from the pins 0 to 5 of port E, pins 1 to 4 of port H,
pins 6 and 7 of port L, as GPIO interrupts.
A GPIO interrupt is a low-active interrupt. Enable interrupt requests after setting the pins
corresponding to the port control register (E, H, and L) used for GPIO interrupts to be input pins
from ports For the port control registers, see section 28, General Purpose I/O Ports (GPIO).
The timing required to reflect the register value is guaranteed by writing to this register, and then,
reading from this register once (the interrupt request is reflected).
Table 10.11 shows the correspondence between bits in INT2GPIC and the functions.
Table 10.11 Correspondence between Bits in INT2GPIC and GPIO Interrupts
Rev.1.00 Jan. 10, 2008 Page 322 of 1658
REJ09B0261-0100
Initial value:
Initial value:
Bit
31 to
26
25
24
23 to
20
19
R/W:
R/W:
Name
⎯
PORTL7E
PORTL6E
⎯
PORTH4E 0
Bit:
Bit:
GPIO Interrupt Set Register (INT2GPIC)
31
15
⎯
⎯
R
R
0
0
30
⎯
14
⎯
R
R
0
0
Initial
Value R/W
All 0
0
0
All 0
29
⎯
13
⎯
R
R
0
0
R/W
R/W
R/W
R/W
R/W
28
12
⎯
⎯
R
R
0
0
Function
Reserved
These bits are always read as 0.
The write value should always be 0.
Enables interrupt request from pin 7
of port L.
Enables interrupt request from pin 6
of port L.
Reserved
These bits are always read as 0.
The write value should always be 0.
Enables interrupt request from pin 4
of port H.
27
11
⎯
⎯
R
R
0
0
R/W
26
10
⎯
R
0
0
R/W
R/W
25
0
9
0
R/W
R/W
24
0
8
0
23
⎯
⎯
R
R
0
7
0
22
⎯
⎯
R
R
0
6
0
21
⎯
⎯
R
R
0
5
0
Description
Enables GPIO interrupt
request for each pin.
0: Disable the
1: Enable the
20
⎯
⎯
R
R
0
4
0
corresponding interrupt
request
corresponding interrupt
request
R/W
19
⎯
R
0
3
0
R/W
R/W
18
0
2
0
R/W
R/W
17
0
1
0
R/W
R/W
16
0
0
0