R8A77850ANBGV Renesas Electronics America, R8A77850ANBGV Datasheet - Page 1506

• Manufacturer Part Number: R8A77850ANBGV
• Description: IC SUPERH MPU ROMLESS 436-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850ANBGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

29. User Break Controller (UBC)
29.3.2
The following describes the sequence from when the break condition is set until the user break
exception handling is initiated.
1. Specify the operand size, bus, instruction fetch/operand access, and read/write as the match
2. Specify whether or not to request a break when the match condition is satisfied and the break
3. When the match condition has been satisfied, the corresponding condition match flag (MF1 or
4. The match flags (MF1 and MF0) can be used to confirm whether or not the corresponding
5. Breaks may occur virtually at the same time for channels 0 and 1. In this case, only one break
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conditions using the match condition setting register (CBR0 or CBR1). Specify the break
address using the match address setting register (CAR0 or CAR1), and specify the address
mask condition using the match address mask setting register (CAMR0 or CAMR1). To
include the ASID in the match conditions, set the AIE bit in the match condition setting
register and specify the ASID value by the AIV bit in the same register. To include the data
value in the match conditions, set the DBE bit in the match condition setting register; specify
the break data using the match data setting register (CDR1); and specify the data mask
condition using the match data mask setting register (CDMR1). To include the execution count
in the match conditions, set the ETBE bit of the match condition setting register; and specify
the execution count using the execution count break register (CETR1). To use the sequential
break, set the MFE bit of the match condition setting register; and specify the number of the
first channel using the MFI bit.
timing when the match condition is satisfied as a result of fetching the instruction using the
match operation setting register (CRR0 or CRR1). After having set all the bits in the match
condition setting register except the CE bit and the other necessary registers, set the CE bit and
read the match condition setting register again. This ensures that the set values in the control
registers are valid for the subsequent instructions immediately after reading the register.
Setting the CE bit of the match condition setting register in the initial state after reset via the
control registers may cause an undesired break.
MF0) in the channel match flag register (CCMFR) is set. A break is also requested to the CPU
according to the set values in the match operation setting register (CRR0 or CRR1). The CPU
operates differently according to the BL bit value of the SR register: when the BL bit is 0, the
CPU accepts the break request and executes the specified exception handling; and when the
BL bit is 1, the CPU does not execute the exception handling.
match condition has been satisfied. Although the flag is set when the condition is satisfied, it is
not cleared automatically; therefore, write 0 to the flag bit by issuing a memory store
instruction to the channel match flag register (CCMFR) in order to use the flag again.
request is sent to the CPU; however, the two condition match flags corresponding to these
breaks may be set.
User Break Operation Sequence