UPD70F3737GF-GAS-AX Renesas Electronics America, UPD70F3737GF-GAS-AX Datasheet - Page 203

• Manufacturer Part Number: UPD70F3737GF-GAS-AX
• Description: MCU 32BIT V850ES/JX3-L 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3737GF-GAS-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

5.7
access of the bus cycle that is executed for each space selected by the memory block in the multiplexed address/data
bus mode. In the separate bus mode, one idle state (TI) can be inserted after the T2 state. By inserting idle states,
the data output float delay time of the memory can be secured during a read access (an idle state cannot be inserted
during a write access).
To realize interfacing with a low-speed device, one idle state (TI) can be inserted after the T3 state only in the read
Whether an idle state is to be inserted can be programmed by using the BCC register.
An idle state is inserted for all the areas immediately after system reset.
(1) Bus cycle control register (BCC)
Idle State Insertion Function
This register can be read or written in 16-bit units.
Reset sets this register to AAAAH.
Cautions 1. The internal ROM, internal RAM, and on-chip peripheral I/O areas are not subject to idle
Memory
block n signal
After reset: AAAAH
BCC
2. Write to the BCC register after reset, and then do not change the set values. Also, when
state insertion.
changing the initial values of the BCC register, do not access an external memory area
until the settings are complete.
Memory block 3
Caution Be sure to set bits 15, 13, 11, and 9 to “1”, and clear bits 14,
BC31
BCn1
15
1
0
1
7
12, 10, 8, 6, 4, 2, and 0 to “0”.
Not inserted
Inserted
14
0
6
0
CHAPTER 5 BUS CONTROL FUNCTION
R/W
Memory block 2
Specifies insertion of idle state (n = 0 to 3)
BC21
User’s Manual U18953EJ5V0UD
13
Address: FFFFF48AH
1
5
12
0
4
0
Memory block 1
BC11
11
1
3
10
0
2
0
Memory block 0
BC01
1
9
1
0
0
8
0
201