UPD70F3737GF-GAS-AX Renesas Electronics America, UPD70F3737GF-GAS-AX Datasheet - Page 767

• Manufacturer Part Number: UPD70F3737GF-GAS-AX
• Description: MCU 32BIT V850ES/JX3-L 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3737GF-GAS-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

<R>
(6) DMA trigger factor registers 0 to 3 (DTFR0 to DTFR3)
Note Do not write 1 to the DFn bit by using software. Write 0 to this bit to clear a DMA transfer request if an
Cautions 1. Set the IFCn5 to IFCn0 bits during one of the following periods in which DMA transfer is
Remark
The DTFR0 to DTFR3 registers are 8-bit registers that control the DMA transfer start trigger via interrupt
request signals from on-chip peripheral I/O.
The interrupt request signals set by these registers serve as DMA transfer start factors.
These registers can be read or written in 8-bit units. However, DFn bit can be read or written in 1-bit units.
Reset sets these registers to 00H.
interrupt specified as the DMA transfer start factor occurs while DMA transfer is disabled.
2. Be sure to follow the steps below when changing the DTFRn register settings. (n = 0 to 3,
3. An interrupt request that is generated in the standby mode (IDLE1, IDLE2, STOP, or sub-
4. If a DMA start factor is selected by the IFCn5 to IFCn0 bits, the DFn bit is set to 1 when an
For the IFCn5 to IFCn0 bits, see Table 20-2 DMA Start Factors.
(n = 0 to 3)
disabled (DCHCn.Enn bit = 0).
m = 0 to 3, n ≠ m)
IDLE mode) does not start the DMA transfer cycle (nor is the DFn bit set to 1).
interrupt from the selected on-chip peripheral I/O occurs, regardless of whether the DMA
transfer is enabled. If DMA is enabled in this status, DMA transfer immediately starts.
• Period from after reset to start of first DMA transfer
• Period from after channel initialization by DCHCn.INITn bit to start of DMA transfer
• Period from after completion of DMA transfer (DCHCn.TCn bit = 1) to start of the next
DTFRn
After reset:
DMA transfer
<1> Stop the DMAn operation of the channel to be rewritten (DCHCn.Enn bit = 0).
<2> Change the DTFRn register settings. (Be sure to set DFn bit = 0 and change the
<3> Confirm that DFn bit = 0.
<4> Enable the DMAn operation (Enn bit = 1).
settings in the 8-bit manipulation.)
beforehand.)
DFn
00H
DFn
<7>
0
1
Note
CHAPTER 20 DMA FUNCTION (DMA CONTROLLER)
No DMA transfer request
DMA transfer request
R/W
0
6
User’s Manual U18953EJ5V0UD
Address:
IFCn5
5
DTFR0 FFFFF810H, DTFR1 FFFFF812H,
DTFR2 FFFFF814H, DTFR3 FFFFF816H
DMA transfer request status flag
IFCn4
(Stop the interrupt generation source operation
4
IFCn3
3
IFCn2
2
IFCn1
1
IFCn0
0
765