UPD70F3737GF-GAS-AX Renesas Electronics America, UPD70F3737GF-GAS-AX Datasheet - Page 644

• Manufacturer Part Number: UPD70F3737GF-GAS-AX
• Description: MCU 32BIT V850ES/JX3-L 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3737GF-GAS-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

642
INTCBnR signal
Remark
CBnTSF bit
SCKBn pin
SOBn pin
(1) Write 00H to the CBnCTL1 register, and select communication type 1, communication clock (f
(2) Write 00H to the CBnCTL2 register, and set the transfer data length to 8 bits.
(3) Write C1H to the CBnCTL0 register, and select the transmission mode and MSB first at the same time
(4) The CBnSTR.CBnTSF bit is set to 1 by writing the transmit data to the CBnTX register, and
(5) When transmission is started, output the serial clock to the SCKBn pin, and output the transmit data
(6) When transmission of data of the transfer data length set by the CBnCTL2 register is completed, stop
(7) To continue transmission, repeat the above steps from (4) after the INTCBnR signal is generated.
(8) To end transmission, clear the CBnCTL0.CBnPWR and CBnCTL0.CBnTXE bits to 0.
f
as enabling the operation of the communication clock (f
transmission is started.
from the SOBn pin in synchronization with the serial clock.
the serial clock output and transmit data output, generate the reception complete interrupt request
signal (INTCBnR) at the last edge of the serial clock cycle, and clear the CBnTSF bit to 0.
Figure 18-6. Single Transfer Mode Operation Timing (Master Mode, Transmission Mode)
XX
n = 0 to 4
/2, and master mode.
(1)
(2)
(3)
(4)
(5)
Bit 7
Bit 6
CHAPTER 18 CLOCKED SERIAL INTERFACE B (CSIB)
Bit 5
Bit 4
Bit 3
User’s Manual U18953EJ5V0UD
Bit 2
Bit 1
(6)
Bit 0
(7)
CCLK
Bit 7 Bit 6
).
Bit 5
Bit 4
Bit 3 Bit 2
Bit 1
Bit 0
(8)
CCLK
) =