UPD70F3737GF-GAS-AX Renesas Electronics America, UPD70F3737GF-GAS-AX Datasheet - Page 595

• Manufacturer Part Number: UPD70F3737GF-GAS-AX
• Description: MCU 32BIT V850ES/JX3-L 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3737GF-GAS-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

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(2) UARTC0 control register 1 (UC0CTL1)
(3) UARTC0 control register 2 (UC0CTL2)
For details, see 17.7 (2) UARTC0 control register 1 (UC0CTL1).
For details, see 17.7 (3) UARTC0 control register 2 (UC0CTL2).
CHAPTER 17 ASYNCHRONOUS SERIAL INTERFACE C (UARTC) (
Remark
• This register is rewritten only when the UC0PWR bit is 0 or the UC0TXE bit and the
• If “Reception with 0 parity” is selected during reception, a parity check is not performed.
• When transmission and reception are performed in the LIN format, clear the
• This register can be rewritten only when the UC0PWR bit is 0 or the UC0TXE bit
• When transmission and reception are performed in the LIN format, set the UC0CL
This register can be rewritten only when the UC0PWR bit is 0 or the UC0TXE bit and
the UC0RXE bit are 0.
• This register can be rewritten only when the UC0PWR bit is 0 or the UC0TXE bit
• When transmission and reception are performed in the LIN format, set the UC0DIR
UC0PS1
UC0DIR
UC0CL
UC0SL
UC0RXE bit are 0.
Therefore, the UC0STR.UC0PE bit is not set.
UC0PS1 and UC0PS0 bits to 00.
and the UC0RXE bit are 0.
bit to 1.
and the UC0RXE bit are 0.
bit to 1.
0
1
0
1
0
1
0
0
1
1
7 bits
8 bits
1 bit
2 bits
MSB first
LSB first
For details of parity, see 17.6.6 Parity types and operations.
UC0PS0
Specification of data character length of 1 frame of transmit/receive data
0
1
0
1
Parity selection during transmission Parity selection during reception
No parity output
0 parity output
Odd parity output
Even parity output
Specification of length of stop bit for transmit data
User’s Manual U18953EJ5V0UD
Data transfer order
Reception with no parity
Reception with 0 parity
Odd parity check
Even parity check
PD70F3792, 70F3793)
(2/2)
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