UPD70F3737GF-GAS-AX Renesas Electronics America, UPD70F3737GF-GAS-AX Datasheet - Page 322

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UPD70F3737GF-GAS-AX

Manufacturer Part Number
UPD70F3737GF-GAS-AX
Description
MCU 32BIT V850ES/JX3-L 100-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Lr
Datasheet

Specifications of UPD70F3737GF-GAS-AX

Core Processor
RISC
Core Size
32-Bit
Speed
20MHz
Connectivity
CSI, EBI/EMI, I²C, UART/USART
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
84
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.2 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
UPD70F3737GF-GAS-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
7.4.7
time it is detected that a valid edge has been input to the TIPna pin, the value of the 16-bit counter is stored in the
TPnCCRa register, and the 16-bit counter is cleared to 0000H.
signal (INTTPnCCa) occurs.
TPnIOC1 register for the unused pins.
320
In the pulse width measurement mode, TMPn starts incrementing when the TPnCTL0.TPnCE bit is set to 1. Each
The interval of the valid edge can be measured by reading the TPnCCRa register after a capture interrupt request
Select either the TIPn0 or TIPn1 pin as the capture trigger input pin. Specify “No edge detected” by using the
Remarks 1. For how to set the TIPn0 and TIPn1 pins, see Table 7-2 Pins Used by TMPn and Table 4-15
Pulse width measurement mode (TPnMD2 to TPnMD0 bits = 110)
trigger input)
trigger input)
TIPn0 pin
TIPn1 pin
(capture
(capture
2. For how to enable the INTTPnCC0 and INTTPnCC1 interrupt signals, see CHAPTER 21
3. a = 0, 1
Settings When Pins Are Used for Alternate Functions.
INTERRUPT SERVICING/EXCEPTION PROCESSING.
n = 0 to 5
Figure 7-65. Configuration of TMPn in Pulse Width Measurement Mode
detector
detector
Edge
Edge
CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP)
selection
TPnCE bit
Count
clock
User’s Manual U18953EJ5V0UD
TPnCCR0 register
(capture)
TPnCCR1 register
Clear
16-bit counter
(capture)
INTTPnOV signal
INTTPnCC0 signal
INTTPnCC1 signal

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