UPD70F3737GF-GAS-AX Renesas Electronics America, UPD70F3737GF-GAS-AX Datasheet - Page 751

• Manufacturer Part Number: UPD70F3737GF-GAS-AX
• Description: MCU 32BIT V850ES/JX3-L 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3737GF-GAS-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

extension codes are used here). During an INTIICn interrupt, the status is confirmed and the following steps are
executed.
The following shows an example of the processing of the slave device by an INTIICn interrupt (it is assumed that no
<1> When a stop condition is detected, communication is terminated.
<2> When a start condition is detected, the address is confirmed. If the address does not match, communication
<3> For data transmission/reception, when the ready flag is set, operation returns from the interrupt while the
Remark
Remark
Interrupt servicing completed
is terminated. If the address matches, the communication mode is set and wait is released, and operation
returns from the interrupt (the ready flag is cleared).
I
2
C0n bus remains in the wait status.
INTIICn occurred
<1> to <3> above correspond to <1> to <3> in Figure 19-22 Slave Operation Flowchart (2).
n = 0 to 2
Set ready flag
SPDn = 1?
STDn = 1?
No
No
<3>
Figure 19-22. Slave Operation Flowchart (2)
Yes
Yes
Communication direction flag ← TRCn
User’s Manual U18953EJ5V0UD
<1>
<2>
Set communication mode flag
CHAPTER 19 I
Clear ready flag
COIn = 1?
Yes
2
C BUS
No
and communication mode flag
direction flag, ready flag,
Clear communication
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