UPD70F3737GF-GAS-AX Renesas Electronics America, UPD70F3737GF-GAS-AX Datasheet - Page 851

• Manufacturer Part Number: UPD70F3737GF-GAS-AX
• Description: MCU 32BIT V850ES/JX3-L 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3737GF-GAS-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

status in the low-voltage subclock operation mode.
(1) Procedure for switching from subclock operation mode to low-voltage subclock operation mode
Table 23-11 shows the operating status in the subclock operation mode and Table 23-12 shows the operating
Make the following settings in the subclock operation mode.
<1> Stop the main clock and PLL.
<2> Stop the functions whose operation is specified as stopped in Table 23-14 Operating Status in Low-
<3> Disable DMA (if DMA is enabled).
<4> • Disable maskable interrupts by using the DI instruction.
<5> Write C9H (enabling data) to the REGPR register.
<6> Write 02H to the REGOVL0 register.
<7> Write 00H (protection data) to the REGPR register.
<8> As necessary, enable maskable interrupts, the NMI interrupt, or the INTWDT2 interrupt by using the EI
Be sure to observe the above sequence.
For the setting of the subclock operation mode, see 23.7.1 Setting and operation status.
Voltage Sub-IDLE Mode.
Be especially sure to stop the following, because they are signals from external sources.
• Stop the SCKBn input clock when the SCKBn input clock to CSIBn is selected (n = 0 to 4).
• Stop the ASCKA0 input clock when the ASCKA0 input clock to UARTA0 is selected.
• Disable the NMI interrupt (INTF02 = 0, INTR02 = 0).
• Create a status in which the INTWDT2 signal is not generated (create a status in which the INTWDT2
At this time, the output voltage of the regulator is at the low level, decreasing power consumption to an
extremely low level.
instruction (restore the setting in <4> above).
signal is not generated immediately after watchdog timer 2 has been cleared).
CHAPTER 23 STANDBY FUNCTION
User’s Manual U18953EJ5V0UD
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