UPD70F3737GF-GAS-AX Renesas Electronics America, UPD70F3737GF-GAS-AX Datasheet - Page 306

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UPD70F3737GF-GAS-AX

Manufacturer Part Number
UPD70F3737GF-GAS-AX
Description
MCU 32BIT V850ES/JX3-L 100-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Lr
Datasheet

Specifications of UPD70F3737GF-GAS-AX

Core Processor
RISC
Core Size
32-Bit
Speed
20MHz
Connectivity
CSI, EBI/EMI, I²C, UART/USART
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
84
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.2 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
UPD70F3737GF-GAS-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
7.4.6
the TPnCCRa register can be used as a compare register or a capture register, according to the setting of the
TPnOPT0.TPnCCS0 and TPnOPT0.TPnCCS1 bits.
304
(external event
TIPn0
TIPn1
trigger input)
trigger input)
In the free-running timer mode, TMPn starts incrementing when the TPnCTL0.TPnCE bit is set to 1. At this time,
Remarks 1. For how to set the TIPn0, TIPn1, TOPn0, and TOPn1 pins, see Table 7-2 Pins Used by TMPn and
count input/
(capture
Note 1
Note 2
capture
Free-running timer mode (TPnMD2 to TPnMD0 bits = 101)
Internal count clock
pin
pin
Notes 1. The external event count input/capture trigger input pin (TIPn0) can also be used as the
Remark
2. For how to enable the INTTPnCC0 and INTTPnCC1 interrupt signals, see CHAPTER 21
3. a = 0, 1
Table 4-15 Settings When Pins Are Used for Alternate Functions.
INTERRUPT SERVICING/EXCEPTION PROCESSING.
n = 0 to 5
2. The capture trigger input pin (TIPn1) can also be used as the timer output pin (TOPn1);
detector
detector
detector
Edge
Edge
Edge
timer output pin (TOPn0); however, only one of these functions can be used at a time.
however, only one of these functions can be used at a time.
a = 0, 1
n = 0 to 5
Figure 7-52. Configuration of TMPn in Free-Running Timer Mode
selection
TPnCE bit
Count
CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP)
clock
User’s Manual U18953EJ5V0UD
TPnCCR0 register
TPnCCR0 register
(compare)
(capture)
TPnCCR1 register
TPnCCR1 register
16-bit counter
(compare)
(capture)
0
1
controller
controller
TPnCCS0, TPnCCS1 bits
(capture/compare selection)
Output
Output
0
1
INTTPnOV signal
INTTPnCC1 signal
INTTPnCC0 signal
TOPn1
TOPn0
Note 2
Note 1
pin output
pin output

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