UPD70F3737GF-GAS-AX Renesas Electronics America, UPD70F3737GF-GAS-AX Datasheet - Page 316

• Manufacturer Part Number: UPD70F3737GF-GAS-AX
• Description: MCU 32BIT V850ES/JX3-L 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3737GF-GAS-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

314
(b) Pulse width measurement using the TPnCCRa register as a capture register
When pulse width measurement is performed with the TPnCCRa register used as a capture register, each
time the INTTPnCCa signal has been detected, the capture register must be read and the interval must be
calculated by software.
When executing pulse width measurement in the free-running timer mode, two pulse widths can be
measured for one channel.
When measuring a pulse width, the pulse width can be calculated by reading the value of the TPnCCRa
register in synchronization with the INTTPnCCa signal, and calculating the difference between that value
and the previously read value.
Remark
(CCR0 buffer register)
(CCR1 buffer register)
INTTPnCC0 signal
INTTPnCC1 signal
TPnCCR0 register
TPnCCR1 register
INTTPnOV signal
Figure 7-59. Pulse Width Measurement by TMPn in Free-Running Timer Mode
TIPn0 pin input
TIPn1 pin input
16-bit counter
TPnOVF bit
TPnCE bit
a = 0, 1
n = 0 to 5
FFFFH
0000H
CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP)
Pulse interval
0000H
0000H
Pulse interval
(D
User’s Manual U18953EJ5V0UD
00
D
)
(D
D
00
10
10
)
Pulse interval
(10000H +
D
D
01
Cleared to 0 by
CLR1 instruction
Pulse interval
00
− D
(10000H +
D
D
00
11
01
)
D
− D
D
10
Pulse interval
11
10
(D
)
02
− D
D
D
Pulse interval
02
01
01
(10000H +
)
D
D
12
Cleared to 0 by
CLR1 instruction
11
− D
Pulse interval
(10000H +
D
D
11
03
12
D
)
− D
D
02
03
02
)
Pulse interval
(10000H +
D
13
Pulse interval
(10000H +
− D
D
04
D
D
D
− D
12
Cleared to 0 by
CLR1 instruction
03
12
13
)
03
)
D
04
D
D
04
13