UPD70F3737GF-GAS-AX Renesas Electronics America, UPD70F3737GF-GAS-AX Datasheet - Page 320

• Manufacturer Part Number: UPD70F3737GF-GAS-AX
• Description: MCU 32BIT V850ES/JX3-L 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3737GF-GAS-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

318
Figure 7-63. Example of Incorrect Processing When Capture Trigger Interval Is Long (When Using TIPn0)
(d) Processing of overflow if capture trigger interval is long
If the pulse width is greater than one cycle of the 16-bit counter, care must be exercised because an
overflow may occur more than once between the first capture trigger and the next. First, an example of
incorrect processing is shown below.
The following problem may occur when long pulse width is measured in the free-running timer mode.
<1> The TPnCCR0 register is read (the default value of the TIPn0 pin input is set).
<2> An overflow occurs. There is no software processing.
<3> An overflow occurs a second time. There is no software processing.
<4> The TPnCCR0 register is read.
If an overflow occurs twice or more when the capture trigger interval is long, the correct pulse width may
not be obtained.
If the capture trigger interval is long, slow the count clock to lengthen one cycle of the 16-bit counter, or
use software to resolve the problem. An example of how to use software to resolve the problem is shown
below.
TPnCCR0 register
INTTPnOV signal
The TPnOVF bit is read. The TPnOVF bit is 1, so it is cleared to 0.
Because the TPnOVF bit was 1, the pulse width can be calculated by (10000H + D
(incorrect).
Actually, the pulse width should be (20000H + D
TIPn0 pin input
16-bit counter
TPnOVF bit
TPnCE bit
FFFFH
0000H
CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP)
User’s Manual U18953EJ5V0UD
D
m0
<1> <2>
a1
− D
1 cycle of 16-bit counter
a0
) because an overflow occurred twice.
Pulse width
D
m0
<3> <4>
D
m1
D
m1
a1
− D
a0
)