UPD70F3737GF-GAS-AX Renesas Electronics America, UPD70F3737GF-GAS-AX Datasheet - Page 965

• Manufacturer Part Number: UPD70F3737GF-GAS-AX
• Description: MCU 32BIT V850ES/JX3-L 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3737GF-GAS-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

32.7.3 Bus timing
satisfied. It is not necessary to satisfy the values for both methods.
(1) In multiplexed bus mode
(a) Read/write cycle (Asynchronous to CLKOUT)
(T
Remarks 1. t
Address setup time (to ASTB↓)
Address hold time (from ASTB↓)
Delay time from RD↓ to address float
Data input setup time from address
Data input setup time from RD↓
Delay time from ASTB↓ to RD, WRm↓
Data input hold time (from RD↑)
Address output time from RD↑
Delay time from RD, WRm↑ to ASTB↑
Delay time from RD↑ to ASTB↓
RD, WRm low-level width
ASTB high-level width
Data output time from WRm↓
Data output setup time (to WRm↑)
Data output hold time (from WRm↑)
WAIT setup time (to address)
WAIT hold time (from address)
WAIT setup time (to ASTB↓)
WAIT hold time (from ASTB↓)
Address hold time from RD↑
Address hold time from WRm↑
A
The values for just the access method to be used (synchronous with or asynchronous to CLKOUT) must be
= −40 to +85°C, V
2. T = 1/f
3. n: Number of wait clocks inserted in the bus cycle
4. m = 0, 1
5. i: Number of idle states inserted after a read cycle (0 or 1)
6. The values in the above specifications are values for when clocks with a 1:1 duty ratio are input from
Parameter
t
The sampling timing changes when a programmable wait is inserted.
X1.
ASW
AHW
: Number of address setup wait clocks (0 or 1)
: Number of address hold wait clocks (0 or 1)
CPU
DD
(f
= EV
CHAPTER 32 ELECTRICAL SPECIFICATIONS (
CPU
: CPU operating clock frequency)
DD
= AV
REF0
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
SAST
HSTA
FRDA
SAID
SRID
DSTRDWR
HRDID
DRDA
DRDWRST
DRDST
WRDWRL
WSTH
DWROD
SODWR
HWROD
SAWT1
SAWT2
HAWT1
HAWT2
SSTWT1
SSTWT2
HSTWT1
HSTWT2
HRDA2
HWRA2
= AV
Symbol
User’s Manual U18953EJ5V0UD
REF1
= 2.7 to 3.6 V, V
<10>
<11>
<12>
<13>
<14>
<15>
<16>
<17>
<18>
<19>
<20>
<21>
<22>
<23>
<24>
<25>
<26>
<27>
<28>
<29>
<30>
<6>
<7>
<8>
<9>
n ≥ 1
n ≥ 1
n ≥ 1
n ≥ 1
Conditions
SS
= EV
PD70F3737, 70F3738)
(1.5
(1 + i
(0.5
(1.5
(0.5 + t
(0.5 + t
(0.5 + t
SS
(1
(1
(1
(1
(1
+
+
+
(n + t
0.5T − 15
+
= AV
n + t
n + t
i + t
+
+
+
+
+
T − 15
T − 15
n + t
MIN.
n)T − 15
n)T − 20
AHW
AHW
i)T − 15
t
i)T − 15
ASW
ASW
0
ASW
ASW
ASW
AHW
SS
)T − 20
)T − 15
)T − 15
AHW
)T − 15
+ t
+ t
)T − 15
)T
= 0 V, C
AHW
AHW
)T
)T
)T
(2
(1.5 + t
(1.5
(1
(1 + t
+
L
+
n + t
(1 + n)T − 25
+
= 50 pF)
n + t
n + t
ASW
ASW
MAX.
AHW
ASW
16
15
AHW
+ t
+ t
+ t
)T − 25
AHW
AHW
AHW
)T − 25
)T − 35
)T − 35
)T − 35
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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