UPD70F3737GF-GAS-AX Renesas Electronics America, UPD70F3737GF-GAS-AX Datasheet - Page 675

• Manufacturer Part Number: UPD70F3737GF-GAS-AX
• Description: MCU 32BIT V850ES/JX3-L 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3737GF-GAS-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Notes 1. The INTCBnT interrupt is set when the data written to the CBnTX register is transferred to the data
Caution In single transfer mode, writing to the CBnTX register with the CBnTSF bit set to 1 is ignored.
2. The INTCBnR interrupt occurs if reception is complete and the next receive data is ready in the
SCKBn pin
SCKBn pin
SIBn capture
Reg-R/W
INTCBnT
interrupt
SIBn capture
SOBn pin
Reg-R/W
INTCBnT
interrupt
SOBn pin
INTCBnR
interrupt
CBnTSF bit
INTCBnR
interrupt
CBnTSF bit
shift register in the continuous transmission or continuous transmission/reception modes. In the
single transmission or single transmission/reception modes, the INTCBnT interrupt request signal is
not generated, but the INTCBnR interrupt request signal is generated at the end of communication.
CBnRX register while reception is enabled. In the single mode, the INTCBnR interrupt request
signal is generated even in the transmission mode, at the end of communication.
This has no effect on the operation during transfer.
For example, if the next data is written to the CBnTX register when DMA is started by
generating the INTCBnR signal, the written data is not transferred because the CBnTSF bit is
set to 1.
Use the continuous transfer mode, not the single transfer mode, for such applications.
Note 1
Note 1
Note 2
Note 2
(iii) Communication type 2 (CBnCKP and CBnDAP bits = 01)
(iv) Communication type 4 (CBnCKP and CBnDAP bits = 11)
CHAPTER 18 CLOCKED SERIAL INTERFACE B (CSIB)
D7
D7
Figure 18-30. Clock Timing (2/2)
User’s Manual U18953EJ5V0UD
D6
D6
D5
D5
D4
D4
D3
D3
D2
D2
D1
D1
D0
D0
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