UPD70F3737GF-GAS-AX Renesas Electronics America, UPD70F3737GF-GAS-AX Datasheet - Page 642

• Manufacturer Part Number: UPD70F3737GF-GAS-AX
• Description: MCU 32BIT V850ES/JX3-L 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3737GF-GAS-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

18.5 Interrupt Request Signals
default, and the priority of the transmission enable interrupt request signal is lower.
640
CSIBn can generate the following two interrupt request signals.
• Reception complete interrupt request signal (INTCBnR)
• Transmission enable interrupt request signal (INTCBnT)
Of these two interrupt request signals, the reception complete interrupt request signal has the higher priority by
(1) Reception complete interrupt request signal (INTCBnR)
(2) Transmission enable interrupt request signal (INTCBnT)
When receive data is transferred to the CBnRX register while reception is enabled, the reception complete
interrupt request signal is generated.
This interrupt request signal can also be generated if an overrun error occurs.
When the reception complete interrupt request signal is acknowledged and the data is read, read the CBnSTR
register to check that the result of reception is not an error.
In the single transfer mode, the INTCBnR interrupt request signal is generated upon completion of
transmission, even when only transmission is executed.
In the continuous transmission or continuous transmission/reception mode, transmit data is transferred from
the CBnTX register and, as soon as writing to CBnTX has been enabled, the transmission enable interrupt
request signal is generated.
In the single transmission and single transmission/reception modes, the INTCBnT interrupt is not generated.
CHAPTER 18 CLOCKED SERIAL INTERFACE B (CSIB)
Table 18-3. Interrupts and Their Default Priority
Reception complete
Transmission enable
Interrupt Request Signal
User’s Manual U18953EJ5V0UD
Priority
High
Low