UPD70F3737GF-GAS-AX Renesas Electronics America, UPD70F3737GF-GAS-AX Datasheet - Page 829

• Manufacturer Part Number: UPD70F3737GF-GAS-AX
• Description: MCU 32BIT V850ES/JX3-L 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3737GF-GAS-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

23.2 Registers
(1) Power save control register (PSC)
The PSC register is an 8-bit register that controls the standby function. The STP bit of this register is used to
specify the standby mode. This register is a special register that can only be written in a specific sequence
(see 3.4.7 Special registers).
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 00H.
Note Standby mode set by STP bit: IDLE1, IDLE2, STOP, or sub-IDLE mode
Cautions 1. Before setting one of the standby modes (excluding the HALT mode), specify
After reset: 00H
PSC
NMI1M
NMI0M
INTM
2. The settings of the NMI1M, NMI0M, and INTM bits are invalid when HALT mode
3. If the NMI1M, NMI0M, or INTM bit is set to 1 at the same time the STP bit is set
STP
0
1
0
1
0
1
0
1
7
0
the mode by using the PSMR.PSM1 and PSMR.PSM0 bits and then set the
STP bit.
is released.
to 1, the setting of NMI1M, NMI0M, or INTM bit becomes invalid. If there is an
unmasked
IDLE1/IDLE2/STOP mode is set, set the bit corresponding to the interrupt
request signal (NMI1M, NMI0M, or INTM) to 1, and then set the STP bit to 1.
Standby mode release by INTWDT2 signal enabled
Standby mode release by INTWDT2 signal disabled
Standby mode release by NMI pin input enabled
Standby mode release by NMI pin input disabled
Standby mode release by maskable interrupt request signal enabled
Standby mode release by maskable interrupt request signal disabled
Normal operation mode
Standby mode
NMI1M
R/W
<6>
Standby mode release control via maskable interrupt request signal
Standby mode release control upon occurrence of INTWDT2 signal
CHAPTER 23 STANDBY FUNCTION
interrupt
Address: FFFFF1FEH
NMI0M
User’s Manual U18953EJ5V0UD
<5>
Standby mode release control by NMI pin input
INTM
request
<4>
Standby mode
signal
3
0
Note
setting
being
2
0
held
STP
<1>
pending
0
0
when
the
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