UPD70F3737GF-GAS-AX Renesas Electronics America, UPD70F3737GF-GAS-AX Datasheet - Page 783

• Manufacturer Part Number: UPD70F3737GF-GAS-AX
• Description: MCU 32BIT V850ES/JX3-L 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3737GF-GAS-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(8) Bus arbitration for CPU
(9) Registers/bits that must not be rewritten during DMA transfer
(10) Be sure to set the following register bits to 0 (n = 0 to 3).
(11) DMA start factor
Because the DMA controller is a higher priority bus master than the CPU, a CPU access that takes place
during DMA transfer is held pending until the DMA transfer cycle is completed and the bus is released to the
CPU.
However, the CPU can access the internal ROM and the internal RAM for which DMA transfer is not being
executed.
• The CPU can access the internal ROM and internal RAM when DMA transfer is being executed between the
• The CPU can access the internal ROM when DMA transfer is being executed between the on-chip peripheral
Set up the following registers during one of the periods below when a DMA transfer is not under execution (n =
0 to 3).
[Registers]
[Timing of setting]
• Bits 14 to 10 of DSAnH register
• Bits 14 to 10 of DDAnH register
• Bits 15, 13 to 8, and 3 to 0 of DADCn register
• Bits 6 to 3 of DCHCn register
Do not start multiple DMA channels with the same start factor. If multiple channels are started with the same
factor, DMA for which a channel has already been set may starts or a DMA channel with a lower priority may
be acknowledged before a DMA channel with a higher priority. The operation cannot be guaranteed in this
case.
• DSAnH, DSAnL, DDAnH, DDAnL, DBCn, and DADCn registers
• DTFRn.IFCn5 to DTFRn.IFCn0 bits
• Period from after reset to start of the first DMA transfer
• Period from after channel initialization to start of DMA transfer
• Period from after completion of DMA transfer (TCn bit = 1) to start of the next DMA transfer
external memory and on-chip peripheral I/O.
I/O and the internal RAM.
CHAPTER 20 DMA FUNCTION (DMA CONTROLLER)
User’s Manual U18953EJ5V0UD
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