MC68HC711E20CFN2

Manufacturer Part NumberMC68HC711E20CFN2
DescriptionIC MCU 20K 2MHZ OTP 52-PLCC
ManufacturerFreescale Semiconductor
SeriesHC11
MC68HC711E20CFN2 datasheets
 


Specifications of MC68HC711E20CFN2

Core ProcessorHC11Core Size8-Bit
Speed2MHzConnectivitySCI, SPI
PeripheralsPOR, WDTNumber Of I /o38
Program Memory Size20KB (20K x 8)Program Memory TypeOTP
Eeprom Size512 x 8Ram Size768 x 8
Voltage - Supply (vcc/vdd)4.5 V ~ 5.5 VData ConvertersA/D 8x8b
Oscillator TypeInternalOperating Temperature-40°C ~ 85°C
Package / Case52-PLCCLead Free Status / RoHS StatusContains lead / RoHS non-compliant
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Page 100/242

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Parallel Input/Output (I/O) Ports
PORTCL is used in the handshake clearing mechanism. When an active edge occurs on the STRA pin,
port C data is latched into the PORTCL register. Reads of this register return the last value latched into
PORTCL and clear STAF flag (following a read of PIOC with STAF set).
Address:
$1007
Bit 7
Read:
DDRC7
Write:
Reset:
0
Figure 6-6. Port C Data Direction Register (DDRC)
DDRC[7:0] — Port C Data Direction Bits
In the 3-state variation of output handshake mode, clear the corresponding DDRC bits. Refer to
10-13. 3-State Variation of Output Handshake Timing Diagram (STRA Enables Output
0 = Input
1 = Output
6.5 Port D
In all modes, port D bits [5:0] can be used either for general-purpose I/O or with the serial communications
interface (SCI) and serial peripheral interface (SPI) subsystems. During reset, port D pins PD[5:0] are
configured as high-impedance inputs (DDRD bits cleared).
Address:
$1008
Bit 7
Read:
0
Write:
Reset:
Alternate Function:
I = Indeterminate after reset
Figure 6-7. Port D Data Register (PORTD)
Address:
$1009
Bit 7
Read:
Write:
Reset:
0
= Unimplemented
Figure 6-8. Port D Data Direction Register (DDRD)
Bits [7:6] — Unimplemented
Always read 0
DDRD[5:0] — Port D Data Direction Bits
When DDRD bit 5 is 1 and MSTR = 1 in SPCR, PD5/SS is a general-purpose output and mode fault
logic is disabled.
0 = Input
1 = Output
100
6
5
4
3
DDRC6
DDRC5
DDRC4
DDRC3
0
0
0
0
6
5
4
0
PD5
PD4
I
I
PD5
PD4
SS
SCK
6
5
4
3
DDRD5
DDRD4
DDRD3
0
0
0
0
M68HC11E Family Data Sheet, Rev. 5.1
2
1
Bit 0
DDRC2
DDRC1
DDRC0
0
0
0
Buffer).
3
2
1
Bit 0
PD3
PD2
PD1
PD0
I
I
I
I
PD3
PD2
PD1
PD0
MOSI
MISO
Tx
RxD
2
1
Bit 0
DDRD2
DDRD1
DDRD0
0
0
0
Freescale Semiconductor
Figure