MC68HC711E20CFN2

Manufacturer Part NumberMC68HC711E20CFN2
DescriptionIC MCU 20K 2MHZ OTP 52-PLCC
ManufacturerFreescale Semiconductor
SeriesHC11
MC68HC711E20CFN2 datasheets
 

Specifications of MC68HC711E20CFN2

Core ProcessorHC11Core Size8-Bit
Speed2MHzConnectivitySCI, SPI
PeripheralsPOR, WDTNumber Of I /o38
Program Memory Size20KB (20K x 8)Program Memory TypeOTP
Eeprom Size512 x 8Ram Size768 x 8
Voltage - Supply (vcc/vdd)4.5 V ~ 5.5 VData ConvertersA/D 8x8b
Oscillator TypeInternalOperating Temperature-40°C ~ 85°C
Package / Case52-PLCCLead Free Status / RoHS StatusContains lead / RoHS non-compliant
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General Description
IRQ must be configured for level-sensitive operation if there is more than
one source of IRQ interrupt.
There should be a single pullup resistor near the MCU interrupt input pin (typically 4.7 kΩ). There must
also be an interlock mechanism at each interrupt source so that the source holds the interrupt line low
until the MCU recognizes and acknowledges the interrupt request. If one or more interrupt sources are
still pending after the MCU services a request, the interrupt line will still be held low and the MCU will be
interrupted again as soon as the interrupt mask bit in the MCU is cleared (normally upon return from an
interrupt). Refer to
Chapter 5 Resets and
V
is the input for the 12-volt nominal programming voltage required for EPROM/OTPROM
PPE
programming. On devices without EPROM/OTPROM, this pin is only an XIRQ input.
During EPROM programming of the MC68HC711E9 device, the V
circuitry may latch-up and be damaged if the input current is not limited to
10 mA. For more information please refer to MC68HC711E9 8-Bit
Microcontroller Unit Mask Set Errata 3 (Freescale document order number
68HC711E9MSE3.
1.4.7 MODA and MODB (MODA/LIR and MODB/V
During reset, MODA and MODB select one of the four operating modes:
Single-chip mode
Expanded mode
Test mode
Bootstrap mode
Refer to
Chapter 2 Operating Modes and On-Chip
After the operating mode has been selected, the load instruction register (LIR) pin provides an open-drain
output to indicate that execution of an instruction has begun. A series of E-clock cycles occurs during
execution of each instruction. The LIR signal goes low during the first E-clock cycle of each instruction
(opcode fetch). This output is provided for assistance in program debugging.
The V
pin is used to input random-access memory (RAM) standby power. When the voltage on this
STBY
pin is more than one MOS threshold (about 0.7 volts) above the V
of the reset logic are powered from this signal rather than the V
retained without V
power applied to the MCU. Reset must be driven low before V
DD
must remain low until V
has been restored to a valid level.
DD
1.4.8 V
and V
RL
RH
These two inputs provide the reference voltages for the analog-to-digital (A/D) converter circuitry:
V
is the low reference, typically 0 Vdc.
RL
V
is the high reference.
RH
For proper A/D converter operation:
V
should be at least 3 Vdc greater than V
RH
V
and V
should be between V
RL
RH
24
NOTE
Interrupts.
CAUTION
)
STBY
Memory.
DD
.
RL
and V
.
SS
DD
M68HC11E Family Data Sheet, Rev. 5.1
pin
PPE
voltage, the internal RAM and part
DD
input. This allows RAM contents to be
is removed and
DD
Freescale Semiconductor