MC68HC711E20CFN2

Manufacturer Part NumberMC68HC711E20CFN2
DescriptionIC MCU 20K 2MHZ OTP 52-PLCC
ManufacturerFreescale Semiconductor
SeriesHC11
MC68HC711E20CFN2 datasheets
 


Specifications of MC68HC711E20CFN2

Core ProcessorHC11Core Size8-Bit
Speed2MHzConnectivitySCI, SPI
PeripheralsPOR, WDTNumber Of I /o38
Program Memory Size20KB (20K x 8)Program Memory TypeOTP
Eeprom Size512 x 8Ram Size768 x 8
Voltage - Supply (vcc/vdd)4.5 V ~ 5.5 VData ConvertersA/D 8x8b
Oscillator TypeInternalOperating Temperature-40°C ~ 85°C
Package / Case52-PLCCLead Free Status / RoHS StatusContains lead / RoHS non-compliant
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Page 169/242

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10.16 MC68L11E9/E20 Expansion Bus Timing Characteristics
Num
Characteristic
Frequency of operation (E-clock frequency)
1
Cycle time
Pulse width, E low, PW
= 1/2 t
2
EL
Pulse width, E high, PW
= 1/2 t
3
EH
4a
E and AS rise time
4b
E and AS fall time
(2) (2)a
9
Address hold time
, t
AH
Non-multiplexed address valid time to E rise
12
t
= PW
–(t
+ 80 ns)
AV
EL
ASD
17
Read data setup time
Read data hold time , max = t
18
19
Write data delay time, t
= 1/8 t
DDW
21
Write data hold time, t
= 1/8 t
DHW
Multiplexed address valid time to E rise
22
t
= PW
–(t
+ 90 ns)
AVM
EL
ASD
Multiplexed address valid time to AS fall
24
t
= PW
–70 ns
ASL
ASH
25
Multiplexed address hold time, t
26
Delay time, E to AS rise, t
ASD
Pulse width, AS high, PW
27
ASH
28
Delay time, AS to E rise, t
ASED
(3)a
MPU address access time
29
t
= t
–(PW
–t
ACCA
CYC
EL
AVM
MPU access time, t
= PW
35
ACCE
Multiplexed address delay (Previous cycle MPU read)
36
(2)a
t
= t
+ 30 ns
MAD
ASD
1. V
= 3.0 Vdc to 5.5 Vdc, V
= 0 Vdc, T
DD
SS
otherwise noted
2. Input clocks with duty cycles other than 50% affect bus performance. Timing parameters affected by input clock duty cycle
are identified by (a) and (b). To recalculate the approximate bus timing values, substitute the following expressions in place
of 1/8 t
in the above formulas, where applicable:
CYC
(a) (1–dc) × 1/4 t
CYC
(b) dc × 1/4 t
CYC
Where:
dc is the decimal value of duty cycle percentage (high time).
Freescale Semiconductor
MC68L11E9/E20 Expansion Bus Timing Characteristics
(1)
–25 ns
CYC
–30 ns
CYC
= 1/8 t
–30 ns
CYC
(2)a
MAD
(2)a
+ 70 ns
CYC
(2)a
–30 ns
CYC
(2)a
(2)b
= 1/8 t
–30 ns
AHL
CYC
(2)a
= 1/8 t
–5 ns
CYC
= 1/4 t
–30 ns
CYC
(2)b
= 1/8 t
–5 ns
CYC
) –t
–t
DSR
f
–t
EH
DSR
= T
to T
, all timing is shown with respect to 20% V
A
L
H
M68HC11E Family Data Sheet, Rev. 5.1
1.0 MHz
2.0 MHz
Symbol
Min
Max
Min
f
dc
1.0
dc
o
t
1000
500
CYC
PW
475
225
EL
PW
470
220
EH
t
25
r
t
25
f
t
95
33
AH
t
275
88
AV
t
30
30
DSR
t
0
150
0
DHR
t
195
DDW
t
95
33
DHW
t
268
78
AVM
t
150
25
ASL
t
95
33
AHL
t
120
58
ASD
PW
220
95
ASH
t
120
58
ASED
t
735
298
ACCA
t
440
ACCE
t
150
88
MAD
and 70% V
DD
Unit
Max
2.0
MHz
ns
ns
ns
25
ns
25
ns
ns
ns
ns
88
ns
133
ns
ns
ns
ns
ns
ns
ns
ns
ns
190
ns
ns
, unless
DD
169