MC68HC711E20CFN2

Manufacturer Part NumberMC68HC711E20CFN2
DescriptionIC MCU 20K 2MHZ OTP 52-PLCC
ManufacturerFreescale Semiconductor
SeriesHC11
MC68HC711E20CFN2 datasheets
 


Specifications of MC68HC711E20CFN2

Core ProcessorHC11Core Size8-Bit
Speed2MHzConnectivitySCI, SPI
PeripheralsPOR, WDTNumber Of I /o38
Program Memory Size20KB (20K x 8)Program Memory TypeOTP
Eeprom Size512 x 8Ram Size768 x 8
Voltage - Supply (vcc/vdd)4.5 V ~ 5.5 VData ConvertersA/D 8x8b
Oscillator TypeInternalOperating Temperature-40°C ~ 85°C
Package / Case52-PLCCLead Free Status / RoHS StatusContains lead / RoHS non-compliant
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located in this ROM at $BFC0–$BFFF. The bootstrap ROM contains a small program which initializes the
serial communications interface (SCI) and allows the user to download a program into on-chip RAM. The
size of the downloaded program can be as large as the size of the on-chip RAM. After a 4-character delay,
or after receiving the character for the highest address in RAM, control passes to the loaded program at
$0000. Refer to
Figure
2-2,
Figure
Use of an external pullup resistor is required when using the SCI transmitter pin because port D pins are
configured for wired-OR operation by the bootloader. In bootstrap mode, the interrupt vectors are directed
to RAM. This allows the use of interrupts through a jump table. Refer to the application note AN1060
entitled
M68HC11 Bootstrap
Mode, that is included in this data book.
2.3 Memory Map
The operating mode determines memory mapping and whether external addresses can be accessed.
Refer to
Figure
2-2,
Figure
2-3,
for each of the three families comprising the M68HC11 E series of MCUs.
Memory locations for on-chip resources are the same for both expanded and single-chip modes. Control
bits in the configuration (CONFIG) register allow EPROM and EEPROM (if present) to be disabled from
the memory map. The RAM is mapped to $0000 after reset. It can be placed at any 4-Kbyte boundary
($x000) by writing an appropriate value to the RAM and I/O map register (INIT). The 64-byte register block
is mapped to $1000 after reset and also can be placed at any 4-Kbyte boundary ($x000) by writing an
appropriate value to the INIT register. If RAM and registers are mapped to the same boundary, the first
64 bytes of RAM will be inaccessible.
Refer to
Figure
2-7, which details the MCU register and control bit assignments. Reset states shown are
for single-chip mode only.
$0000
EXT
$1000
$B600
EXT
$D000
$FFFF
EXPANDED
BOOTSTRAP
Figure 2-2. Memory Map for MC68HC11E0
Freescale Semiconductor
2-3,
Figure
2-4,
Figure
2-5, and
Figure
2-4,
Figure
2-5, and
Figure
0000
EXT
01FF
1000
103F
EXT
BF00
BFFF
FFC0
FFFF
SPECIAL
TEST
M68HC11E Family Data Sheet, Rev. 5.1
Memory Map
Figure
2-6.
2-6, which illustrate the memory maps
512 BYTES RAM
64-BYTE REGISTER BLOCK
BOOT
BFC0
SPECIAL MODES
ROM
INTERRUPT
VECTORS
BFFF
NORMAL
MODES
INTERRUPT
VECTORS
31