MC68HC711E20CFN2

Manufacturer Part NumberMC68HC711E20CFN2
DescriptionIC MCU 20K 2MHZ OTP 52-PLCC
ManufacturerFreescale Semiconductor
SeriesHC11
MC68HC711E20CFN2 datasheets
 

Specifications of MC68HC711E20CFN2

Core ProcessorHC11Core Size8-Bit
Speed2MHzConnectivitySCI, SPI
PeripheralsPOR, WDTNumber Of I /o38
Program Memory Size20KB (20K x 8)Program Memory TypeOTP
Eeprom Size512 x 8Ram Size768 x 8
Voltage - Supply (vcc/vdd)4.5 V ~ 5.5 VData ConvertersA/D 8x8b
Oscillator TypeInternalOperating Temperature-40°C ~ 85°C
Package / Case52-PLCCLead Free Status / RoHS StatusContains lead / RoHS non-compliant
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At the end of the interrupt service routine, an return-from interrupt (RTI) instruction is executed. The RTI
instruction causes the saved registers to be pulled off the stack in reverse order. Program execution
resumes at the return address.
Certain instructions push and pull the A and B accumulators and the X and Y index registers and are often
used to preserve program context. For example, pushing accumulator A onto the stack when entering a
subroutine that uses accumulator A and then pulling accumulator A off the stack just before leaving the
subroutine ensures that the contents of a register will be the same after returning from the subroutine as
it was before starting the subroutine.
JSR, JUMP TO SUBROUTINE
MAIN PROGRAM
PC
$9D = JSR
dd
DIRECT
NEXT MAIN INSTR.
RTN
MAIN PROGRAM
PC
$AD = JSR
ff
INDEXED, X
NEXT MAIN INSTR.
RTN
MAIN PROGRAM
PC
$18 = PRE
INDEXED, Y
$AD = JSR
ff
RTN
NEXT MAIN INSTR.
MAIN PROGRAM
PC
$BD = PRE
hh
INDEXED, Y
ll
RTN
NEXT MAIN INSTR.
BSR, BRANCH TO SUBROUTINE
MAIN PROGRAM
È
PC
SP–2
$8D = BSR
SP–1
SP
RTS, RETURN FROM
SUBROUTINE
MAIN PROGRAM
PC
$39 = RTS
SP
SP+1
È
SP+2
Freescale Semiconductor
RTI, RETURN FROM INTERRUPT
INTERRUPT ROUTINE
PC
STACK
7
0
È
SP–2
RTN
SP–1
H
RTN
SP
L
SWI, SOFTWARE INTERRUPT
PC
WAI, WAIT FOR INTERRUPT
PC
STACK
7
0
LEGEND:
RTN
RTN = ADDRESS OF NEXT INSTRUCTION IN MAIN PROGRAM TO
H
RTN
BE EXECUTED UPON RETURN FROM SUBROUTINE
L
RTN
= MOST SIGNIFICANT BYTE OF RETURN ADDRESS
H
RTN
= LEAST SIGNIFICANT BYTE OF RETURN ADDRESS
L
È = STACK POINTER POSITION AFTER OPERATION IS COMPLETE
dd = 8-BIT DIRECT ADDRESS ($0000–$00FF) (HIGH BYTE ASSUMED
STACK
TO BE $00)
7
0
ff = 8-BIT POSITIVE OFFSET $00 (0) TO $FF (255) IS ADDED TO INDEX
hh = HIGH-ORDER BYTE OF 16-BIT EXTENDED ADDRESS
ll = LOW-ORDER BYTE OF 16-BIT EXTENDED ADDRESS
RTN
H
rr= SIGNED RELATIVE OFFSET $80 (–128) TO $7F (+127) (OFFSET
RTN
L
RELATIVE TO THE ADDRESS FOLLOWING THE MACHINE CODE
OFFSET BYTE)
Figure 4-2. Stacking Operations
M68HC11E Family Data Sheet, Rev. 5.1
CPU Registers
STACK
7
$3B = RTI
SP
SP+1
CCR
ACCB
SP+2
ACCA
SP+3
IX
SP+4
H
SP+5
IX
L
SP+6
IY
H
IY
SP+7
L
RTN
SP+8
H
È
RTN
SP+9
L
STACK
MAIN PROGRAM
7
È
SP–9
$3F = SWI
CCR
SP–8
ACCB
SP–7
SP–6
ACCA
SP–5
IX
H
IX
SP–4
L
MAIN PROGRAM
IY
SP–3
H
$3E = WAI
SP–2
IY
L
SP–1
RTN
H
RTN
SP
L
0
0
67