MC68HC711E20CFN2

Manufacturer Part NumberMC68HC711E20CFN2
DescriptionIC MCU 20K 2MHZ OTP 52-PLCC
ManufacturerFreescale Semiconductor
SeriesHC11
MC68HC711E20CFN2 datasheets
 

Specifications of MC68HC711E20CFN2

Core ProcessorHC11Core Size8-Bit
Speed2MHzConnectivitySCI, SPI
PeripheralsPOR, WDTNumber Of I /o38
Program Memory Size20KB (20K x 8)Program Memory TypeOTP
Eeprom Size512 x 8Ram Size768 x 8
Voltage - Supply (vcc/vdd)4.5 V ~ 5.5 VData ConvertersA/D 8x8b
Oscillator TypeInternalOperating Temperature-40°C ~ 85°C
Package / Case52-PLCCLead Free Status / RoHS StatusContains lead / RoHS non-compliant
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Resets and Interrupts
Any one of these interrupts can be assigned the highest maskable interrupt priority by writing the
appropriate value to the PSEL bits in the HPRIO register. Otherwise, the priority arrangement remains the
same. An interrupt that is assigned highest priority is still subject to global masking by the I bit in the CCR,
or by any associated local bits. Interrupt vectors are not affected by priority assignment. To avoid race
conditions, HPRIO can be written only while I-bit interrupts are inhibited.
5.4.1 Highest Priority Interrupt and Miscellaneous Register
Address:
$103C
Bit 7
Read:
(1)
RBOOT
Write:
Reset:
Single chip:
0
Expanded:
0
Bootstrap:
1
Special test:
0
1. The values of the RBOOT, SMOD, and MDA reset bits depend on the mode selected at the
RESET pin rising edge. Refer to
Figure 5-4. Highest Priority I-Bit Interrupt
RBOOT — Read Bootstrap ROM Bit
Has meaning only when the SMOD bit is a 1 (bootstrap mode or special test mode). At all other times
this bit is clear and cannot be written. Refer to
more information.
SMOD — Special Mode Select Bit
This bit reflects the inverse of the MODB input pin at the rising edge of reset. Refer to
Operating Modes and On-Chip Memory
MDA — Mode Select A Bit
The mode select A bit reflects the status of the MODA input pin at the rising edge of reset. Refer to
Chapter 2 Operating Modes and On-Chip Memory
IRVNE — Internal Read Visibility/Not E Bit
The IRVNE control bit allows internal read accesses to be available on the external data bus during
operation in expanded modes. In single-chip and bootstrap modes, IRVNE determines whether the E
clock is driven out an external pin. For the MC68HC811E2, this bit is IRV and only controls internal
read visibility. Refer to
Chapter 2 Operating Modes and On-Chip Memory
PSEL[3:0] — Priority Select Bits
These bits select one interrupt source to be elevated above all other I-bit-related sources and can be
written only while the I bit in the CCR is set (interrupts disabled).
86
6
5
4
3
(1)
(1)
SMOD
MDA
IRVNE
PSEL2
0
0
0
0
0
1
0
0
1
0
0
0
1
1
1
0
Table 2-1. Hardware Mode Select
and Miscellaneous Register (HPRIO)
Chapter 2 Operating Modes and On-Chip Memory
for more information.
for more information.
M68HC11E Family Data Sheet, Rev. 5.1
2
1
Bit 0
PSEL2
PSEL1
PSEL0
1
1
0
1
1
0
1
1
0
1
1
0
Summary.
Chapter 2
for more information.
Freescale Semiconductor
for