MC68HC711E20CFN2

Manufacturer Part NumberMC68HC711E20CFN2
DescriptionIC MCU 20K 2MHZ OTP 52-PLCC
ManufacturerFreescale Semiconductor
SeriesHC11
MC68HC711E20CFN2 datasheets
 

Specifications of MC68HC711E20CFN2

Core ProcessorHC11Core Size8-Bit
Speed2MHzConnectivitySCI, SPI
PeripheralsPOR, WDTNumber Of I /o38
Program Memory Size20KB (20K x 8)Program Memory TypeOTP
Eeprom Size512 x 8Ram Size768 x 8
Voltage - Supply (vcc/vdd)4.5 V ~ 5.5 VData ConvertersA/D 8x8b
Oscillator TypeInternalOperating Temperature-40°C ~ 85°C
Package / Case52-PLCCLead Free Status / RoHS StatusContains lead / RoHS non-compliant
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Page 162/242

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Electrical Characteristics
10.11 Peripheral Port Timing
(1) (2)
Characteristic
Frequency of operation
E-clock frequency
E-clock period
Peripheral data setup time
MCU read of ports A, C, D, and E
Peripheral data hold time
MCU read of ports A, C, D, and E
Delay time, peripheral data write
t
= 1/4 t
+ 100 ns
PWD
CYC
MCU writes to port A
MCU writes to ports B, C, and D
Port C input data setup time
Port C input data hold time
Delay time, E fall to STRB
t
= 1/4 t
+ 100 ns
DEB
CYC
(3)
Setup time, STRA asserted to E fall
Delay time, STRA asserted to port C data output valid
Hold time, STRA negated to port C data
3-state hold time
= 5.0 Vdc ± 10%, V
1. V
= 0 Vdc, T
DD
SS
otherwise noted
2. Ports C and D timing is valid for active drive. (CWOM and DWOM bits are not set in PIOC and SPCR registers, respec-
tively.)
3. If this setup time is met, STRB acknowledges in the next cycle. If it is not met, the response may be delayed one more cycle.
162
1.0 MHz
Symbol
Min
Max
f
dc
1.0
o
t
1000
CYC
t
100
PDSU
t
50
PDH
t
PWD
200
350
t
60
IS
t
100
IH
t
350
DEB
t
0
AES
t
100
PCD
t
10
PCH
t
150
PCZ
= T
to T
, all timing is shown with respect to 20% V
A
L
H
M68HC11E Family Data Sheet, Rev. 5.1
2.0 MHz
3.0 MHz
Unit
Min
Max
Min
Max
dc
2.0
dc
3.0
MHz
500
333
ns
100
100
ns
50
50
ns
ns
200
200
225
183
60
60
ns
100
100
ns
225
183
ns
0
0
ns
100
100
ns
10
10
ns
150
150
ns
and 70% V
, unless
DD
DD
Freescale Semiconductor