MC68HC711E20CFN2

Manufacturer Part NumberMC68HC711E20CFN2
DescriptionIC MCU 20K 2MHZ OTP 52-PLCC
ManufacturerFreescale Semiconductor
SeriesHC11
MC68HC711E20CFN2 datasheets
 

Specifications of MC68HC711E20CFN2

Core ProcessorHC11Core Size8-Bit
Speed2MHzConnectivitySCI, SPI
PeripheralsPOR, WDTNumber Of I /o38
Program Memory Size20KB (20K x 8)Program Memory TypeOTP
Eeprom Size512 x 8Ram Size768 x 8
Voltage - Supply (vcc/vdd)4.5 V ~ 5.5 VData ConvertersA/D 8x8b
Oscillator TypeInternalOperating Temperature-40°C ~ 85°C
Package / Case52-PLCCLead Free Status / RoHS StatusContains lead / RoHS non-compliant
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Resets and Interrupts
5.3.2 Memory Map
After reset, the INIT register is initialized to $01, mapping the RAM at $00 and the control registers at
$1000.
For the MC68HC811E2, the CONFIG register resets to $FF. EEPROM mapping bits (EE[3:0]) place the
EEPROM at $F800. Refer to the memory map diagram for MC68HC811E2 in
Chapter 2 Operating Modes
and On-Chip
Memory.
5.3.3 Timer
During reset, the timer system is initialized to a count of $0000. The prescaler bits are cleared, and all
output compare registers are initialized to $FFFF. All input capture registers are indeterminate after reset.
The output compare 1 mask (OC1M) register is cleared so that successful OC1 compares do not affect
any I/O pins. The other four output compares are configured so that they do not affect any I/O pins on
successful compares. All input capture edge-detector circuits are configured for capture disabled
operation. The timer overflow interrupt flag and all eight timer function interrupt flags are cleared. All nine
timer interrupts are disabled because their mask bits have been cleared.
The I4/O5 bit in the PACTL register is cleared to configure the I4/O5 function as OC5; however, the
OM5:OL5 control bits in the TCTL1 register are clear so OC5 does not control the PA3 pin.
5.3.4 Real-Time Interrupt (RTI)
The real-time interrupt flag (RTIF) is cleared and automatic hardware interrupts are masked. The rate
control bits are cleared after reset and can be initialized by software before the real-time interrupt (RTI)
system is used.
5.3.5 Pulse Accumulator
The pulse accumulator system is disabled at reset so that the pulse accumulator input (PAI) pin defaults
to being a general-purpose input pin.
5.3.6 Computer Operating Properly (COP)
The COP watchdog system is enabled if the NOCOP control bit in the CONFIG register is cleared and
disabled if NOCOP is set. The COP rate is set for the shortest duration timeout.
5.3.7 Serial Communications Interface (SCI)
The reset condition of the SCI system is independent of the operating mode. At reset, the SCI baud rate
control register (BAUD) is initialized to $04. All transmit and receive interrupts are masked and both the
transmitter and receiver are disabled so the port pins default to being general-purpose I/O lines. The SCI
frame format is initialized to an 8-bit character size. The send break and receiver wakeup functions are
disabled. The TDRE and TC status bits in the SCI status register (SCSR) are both 1s, indicating that there
is no transmit data in either the transmit data register or the transmit serial shift register. The RDRF, IDLE,
OR, NF, FE, PF, and RAF receive-related status bits in the SCI control register 2 (SCCR2) are cleared.
5.3.8 Serial Peripheral Interface (SPI)
The SPI system is disabled by reset. The port pins associated with this function default to being
general-purpose I/O lines.
M68HC11E Family Data Sheet, Rev. 5.1
84
Freescale Semiconductor