MC68HC711E20CFN2

Manufacturer Part NumberMC68HC711E20CFN2
DescriptionIC MCU 20K 2MHZ OTP 52-PLCC
ManufacturerFreescale Semiconductor
SeriesHC11
MC68HC711E20CFN2 datasheets
 

Specifications of MC68HC711E20CFN2

Core ProcessorHC11Core Size8-Bit
Speed2MHzConnectivitySCI, SPI
PeripheralsPOR, WDTNumber Of I /o38
Program Memory Size20KB (20K x 8)Program Memory TypeOTP
Eeprom Size512 x 8Ram Size768 x 8
Voltage - Supply (vcc/vdd)4.5 V ~ 5.5 VData ConvertersA/D 8x8b
Oscillator TypeInternalOperating Temperature-40°C ~ 85°C
Package / Case52-PLCCLead Free Status / RoHS StatusContains lead / RoHS non-compliant
MC711E9CFNE2R PDF datasheetMC68HC711E9CFNE3 PDF datasheet #2
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Page 78/242

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Central Processor Unit (CPU)
Table 4-2. Instruction Set (Sheet 7 of 7)
Mnemonic
Operation
Description
TSTA
Test A for Zero
A – 0
or Minus
TSTB
Test B for Zero
B – 0
or Minus
SP + 1 ⇒ IX
TSX
Transfer Stack
Pointer to X
SP + 1 ⇒ IY
TSY
Transfer Stack
Pointer to Y
IX – 1 ⇒ SP
TXS
Transfer X to
Stack Pointer
IY – 1 ⇒ SP
TYS
Transfer Y to
Stack Pointer
WAI
Wait for
Stack Regs & WAIT
Interrupt
IX ⇒ D, D ⇒ IX
XGDX
Exchange D
with X
IY ⇒ D, D ⇒ IY
XGDY
Exchange D
with Y
Cycle
*
Infinity or until reset occurs
**
12 cycles are used beginning with the opcode fetch. A wait state is entered which remains in effect for an integer number of MPU E-clock
cycles (n) until an interrupt is recognized. Finally, two additional cycles are used to fetch the appropriate interrupt vector (14 + n total).
Operands
= 8-bit direct address ($0000–$00FF) (high byte assumed to be $00)
dd
= 8-bit positive offset $00 (0) to $FF (255) (is added to index)
ff
= High-order byte of 16-bit extended address
hh
= One byte of immediate data
ii
= High-order byte of 16-bit immediate data
jj
= Low-order byte of 16-bit immediate data
kk
= Low-order byte of 16-bit extended address
ll
= 8-bit mask (set bits to be affected)
mm
= Signed relative offset $80 (–128) to $7F (+127)
rr
(offset relative to address following machine code offset byte))
Operators
( )
Contents of register shown inside parentheses
⇐
Is transferred to
⇑
Is pulled from stack
⇓
Is pushed onto stack
•
Boolean AND
+
Arithmetic addition symbol except where used as inclusive-OR symbol
in Boolean formula
⊕
Exclusive-OR
∗
Multiply
:
Concatenation
–
Arithmetic subtraction symbol or negation symbol (two’s complement)
78
Addressing
Instruction
Mode
Opcode
Operand
A
INH
4D
—
B
INH
5D
—
INH
30
—
INH
18
30
—
INH
35
—
INH
18
35
—
INH
3E
—
INH
8F
—
INH
18
8F
—
Condition Codes
—
0
1
∆
↓
M68HC11E Family Data Sheet, Rev. 5.1
Condition Codes
Cycles
S
X
H
I
N
Z
V
∆
∆
2
—
—
—
—
0
∆
∆
2
—
—
—
—
0
3
—
—
—
—
—
—
—
4
—
—
—
—
—
—
—
3
—
—
—
—
—
—
—
4
—
—
—
—
—
—
—
**
—
—
—
—
—
—
—
3
—
—
—
—
—
—
—
4
—
—
—
—
—
—
—
Bit not changed
Bit always cleared
Bit always set
Bit cleared or set, depending on operation
Bit can be cleared, cannot become set
Freescale Semiconductor
C
0
0
—
—
—
—
—
—
—

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