MC68HC711E20CFN2

Manufacturer Part NumberMC68HC711E20CFN2
DescriptionIC MCU 20K 2MHZ OTP 52-PLCC
ManufacturerFreescale Semiconductor
SeriesHC11
MC68HC711E20CFN2 datasheets
 

Specifications of MC68HC711E20CFN2

Core ProcessorHC11Core Size8-Bit
Speed2MHzConnectivitySCI, SPI
PeripheralsPOR, WDTNumber Of I /o38
Program Memory Size20KB (20K x 8)Program Memory TypeOTP
Eeprom Size512 x 8Ram Size768 x 8
Voltage - Supply (vcc/vdd)4.5 V ~ 5.5 VData ConvertersA/D 8x8b
Oscillator TypeInternalOperating Temperature-40°C ~ 85°C
Package / Case52-PLCCLead Free Status / RoHS StatusContains lead / RoHS non-compliant
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Main Bootloader Program
[6]
$FF CHARACTER
START
BIT 0
@ 7812 BAUD
Rx DATA SAMPLES
S
0
1
[1]
$FF CHARACTER
@ 1200 BAUD
Rx DATA SAMPLES
( FOR 7812 BAUD )
S
0
0
[7]
Figure 2. Automatic Detection of Baud Rate
Samples taken at [7] detect the failing edge of the start bit and verify it is a logic 0. Samples taken at the
middle of what the receiver interprets as the first five bit times [8] detect logic 0s. The sample taken at the
middle of what the receiver interprets as bit 5 [9] may detect either a 0 or a 1 because the receive data
has a rising transition at about this time. The samples for bits 6 and 7 detect 1s, causing the receiver to
think the received character was $C0 or $E0 [10] at 7812 baud instead of the $FF which was sent at 1200
baud. The stop bit sample detects a 1 as expected [11], but this detection is actually in the middle of bit
0 of the 1200 baud $FF character. The SCI receiver is not confused by the rest of the 1200 baud $FF
character because the receive data line is high [12] just as it would be for the idle condition. If a character
other than $FF is sent as the first character, an SCI receive error could result.
Main Bootloader Program
Figure 3
is a flowchart of the main bootloader program in the MC68HC711E9. This bootloader
demonstrates the most important features of the bootloaders used on all M68HC11 Family members. For
complete listings of other M68HC11 versions, refer to
end of this application note, and to Appendix B of the M68HC11 Reference Manual, Freescale document
order number M68HC11RM/AD.
The reset vector in the boot ROM points to the start [1] of this program. The initialization block [2]
establishes starting conditions and sets up the SCI and port D. The stack pointer is set because there are
push and pull instructions in the bootloader program. The X index register is pointed at the start of the
register block ($1000) so indexed addressing can be used. Indexed addressing takes one less byte of
ROM space than extended instructions, and bit manipulation instructions are not available in extended
addressing forms. The port D wire-OR mode (DWOM) bit in the serial peripheral interface control register
(SPCR) is set to configure port D for wired-OR operation to minimize potential conflicts with external
systems that use the PD1/TxD pin as an input. The baud rate for the SCI is initially set to 7812 baud at a
2-MHz E-clock rate but can automatically switch to 1200 baud based on the first character received. The
SCI receiver and transmitter are enabled. The receiver is required by the bootloading process, and the
transmitter is used to transmit data back to the host computer for optional verification. The last item in the
initialization is to set an intercharacter delay constant used to terminate the download when the host
computer stops sending data to the MC68HC711E9. This delay constant is stored in the timer output
compare 1 (TOC1) register, but the on-chip timer is not used in the bootloader program. This example
198
BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
1
1
1
1
1
1
[2]
$FF
[5]
START
[8]
0
0
0
0
?
1
[9]
$C0
or $E0
[10]
Listing 3. MC68HC711E9 Bootloader ROM
M68HC11 Bootstrap Mode, Rev. 1.1
[4]
BIT 7
STOP
Tx DATA LINE IDLES HIGH
[3]
1
1
BIT 0
BIT 1
[12]
[11]
1
1
Freescale Semiconductor
at the