MC68HC711E20CFN2

Manufacturer Part NumberMC68HC711E20CFN2
DescriptionIC MCU 20K 2MHZ OTP 52-PLCC
ManufacturerFreescale Semiconductor
SeriesHC11
MC68HC711E20CFN2 datasheets
 

Specifications of MC68HC711E20CFN2

Core ProcessorHC11Core Size8-Bit
Speed2MHzConnectivitySCI, SPI
PeripheralsPOR, WDTNumber Of I /o38
Program Memory Size20KB (20K x 8)Program Memory TypeOTP
Eeprom Size512 x 8Ram Size768 x 8
Voltage - Supply (vcc/vdd)4.5 V ~ 5.5 VData ConvertersA/D 8x8b
Oscillator TypeInternalOperating Temperature-40°C ~ 85°C
Package / Case52-PLCCLead Free Status / RoHS StatusContains lead / RoHS non-compliant
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When this control bit is clear, the four requested conversions are performed once to fill the four result
registers. When this control bit is set, conversions are performed continuously with the result registers
updated as data becomes available.
MULT — Multiple Channel/Single Channel Control Bit
When this bit is clear, the A/D converter system is configured to perform four consecutive conversions
on the single channel specified by the four channel select bits CD:CA (bits [3:0] of the ADCTL register).
When this bit is set, the A/D system is configured to perform a conversion on each of four channels
where each result register corresponds to one channel.
When the multiple-channel continuous scan mode is used, extra care is
needed in the design of circuitry driving the A/D inputs. The charge on the
capacitive DAC array before the sample time is related to the voltage on the
previously converted channel. A charge share situation exists between the
internal DAC capacitance and the external circuit capacitance. Although
the amount of charge involved is small, the rate at which it is repeated is
every 64 µs for an E clock of 2 MHz. The RC charging rate of the external
circuit must be balanced against this charge sharing effect to avoid errors
in accuracy. Refer to M68HC11 Reference Manual, Freescale document
order number M68HC11RM/AD, for further information.
CD:CA — Channel Selects D:A Bits
Refer to
Table
3-2. When a multiple channel mode is selected (MULT = 1), the two least significant
channel select bits (CB and CA) have no meaning and the CD and CC bits specify which group of four
channels is to be converted.
Table 3-2. A/D Converter Channel Selection
Channel Select
Control Bits
CD:CC:CB:CA
10XX
1. Used for factory testing
Freescale Semiconductor
NOTE
Channel Signal
0000
AN0
0001
AN1
0010
AN2
0011
AN3
0100
AN4
0101
AN5
0110
AN6
0111
AN7
Reserved
(1)
1100
V
RH
(1)
1101
V
RL
(1)
1110
(V
)/2
RH
(1)
1111
Reserved
M68HC11E Family Data Sheet, Rev. 5.1
A/D Control/Status Register
Result in ADRx
if MULT = 1
ADR1
ADR2
ADR3
ADR4
ADR1
ADR2
ADR3
ADR4
ADR1
ADR2
ADR3
ADR4
63