MC68HC711E20CFN2

Manufacturer Part NumberMC68HC711E20CFN2
DescriptionIC MCU 20K 2MHZ OTP 52-PLCC
ManufacturerFreescale Semiconductor
SeriesHC11
MC68HC711E20CFN2 datasheets
 

Specifications of MC68HC711E20CFN2

Core ProcessorHC11Core Size8-Bit
Speed2MHzConnectivitySCI, SPI
PeripheralsPOR, WDTNumber Of I /o38
Program Memory Size20KB (20K x 8)Program Memory TypeOTP
Eeprom Size512 x 8Ram Size768 x 8
Voltage - Supply (vcc/vdd)4.5 V ~ 5.5 VData ConvertersA/D 8x8b
Oscillator TypeInternalOperating Temperature-40°C ~ 85°C
Package / Case52-PLCCLead Free Status / RoHS StatusContains lead / RoHS non-compliant
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
Page 131
132
Page 132
133
Page 133
134
Page 134
135
Page 135
136
Page 136
137
Page 137
138
Page 138
139
Page 139
140
Page 140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
Page 131/242

Download datasheet (2Mb)Embed
PrevNext
The control and status bits that implement the input capture functions are contained in:
Pulse accumulator control register (PACTL)
Timer control 2 register (TCTL2)
Timer interrupt mask 1 register (TMSK1)
Timer interrupt flag 2 register (TFLG1)
To configure port A bit 3 as an input capture, clear the DDRA3 bit of the PACTL register. Note that this bit
is cleared out of reset. To enable PA3 as the fourth input capture, set the I4/O5 bit in the PACTL register.
Otherwise, PA3 is configured as a fifth output compare out of reset, with bit I4/O5 being cleared. If the
DDRA3 bit is set (configuring PA3 as an output), and IC4 is enabled, then writes to PA3 cause edges on
the pin to result in input captures. Writing to TI4/O5 has no effect when the TI4/O5 register is acting as IC4.
9.3.1 Timer Control Register 2
Use the control bits of this register to program input capture functions to detect a particular edge polarity
on the corresponding timer input pin. Each of the input capture functions can be independently configured
to detect rising edges only, falling edges only, any edge (rising or falling), or to disable the input capture
function. The input capture functions operate independently of each other and can capture the same
TCNT value if the input edges are detected within the same timer count cycle.
Address:
$1021
Bit 7
Read:
EDG4B
Write:
Reset:
0
Figure 9-3. Timer Control Register 2 (TCTL2)
EDGxB and EDGxA — Input Capture Edge Control Bits
There are four pairs of these bits. Each pair is cleared to 0 by reset and must be encoded to configure
the corresponding input capture edge detector circuit. IC4 functions only if the I4/O5 bit in the PACTL
register is set. Refer to
Table 9-2
EDGxB
9.3.2 Timer Input Capture Registers
When an edge has been detected and synchronized, the 16-bit free-running counter value is transferred
into the input capture register pair as a single 16-bit parallel transfer. Timer counter value captures and
timer counter incrementing occur on opposite half-cycles of the phase 2 clock so that the count value is
stable whenever a capture occurs. The timer input capture registers are not affected by reset. Input
capture values can be read from a pair of 8-bit read-only registers. A read of the high-order byte of an
Freescale Semiconductor
6
5
4
3
EDG4A
EDG1B
EDG1A
EDG2B
0
0
0
0
for timer control configuration.
Table 9-2. Timer Control Configuration
EDGxA
Configuration
0
0
Capture disabled
0
1
Capture on rising edges only
1
0
Capture on falling edges only
1
1
Capture on any edge
M68HC11E Family Data Sheet, Rev. 5.1
Input Capture
2
1
Bit 0
EDG2A
EDG3B
EDG3A
0
0
0
131