MC68HC711E20CFN2

Manufacturer Part NumberMC68HC711E20CFN2
DescriptionIC MCU 20K 2MHZ OTP 52-PLCC
ManufacturerFreescale Semiconductor
SeriesHC11
MC68HC711E20CFN2 datasheets
 


Specifications of MC68HC711E20CFN2

Core ProcessorHC11Core Size8-Bit
Speed2MHzConnectivitySCI, SPI
PeripheralsPOR, WDTNumber Of I /o38
Program Memory Size20KB (20K x 8)Program Memory TypeOTP
Eeprom Size512 x 8Ram Size768 x 8
Voltage - Supply (vcc/vdd)4.5 V ~ 5.5 VData ConvertersA/D 8x8b
Oscillator TypeInternalOperating Temperature-40°C ~ 85°C
Package / Case52-PLCCLead Free Status / RoHS StatusContains lead / RoHS non-compliant
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Addr.
Register Name
Timer Interrupt Flag 2
$1025
(TFLG2)
See page 142.
Pulse Accumulator Control Regis-
$1026
ter (PACTL)
See page 142.
Pulse Accumulator Count Regis-
$1027
ter (PACNT)
See page 146.
Serial Peripheral Control Register
$1028
(SPCR)
See page 123.
Serial Peripheral Status Register
$1029
(SPSR)
See page 124.
Serial Peripheral Data I/O Regis-
$102A
ter (SPDR)
See page 125.
Baud Rate Register
$102B
(BAUD)
See page 113.
Serial Communications Control
$102C
Register 1 (SCCR1)
See page 110.
Serial Communications Control
$102D
Register 2 (SCCR2)
See page 111.
Serial Communications Status
$102E
Register (SCSR)
See page 112.
1. SCP2 adds ÷39 to SCI prescaler and is present only in MC68HC(7)11E20.
Serial Communications Data Reg-
$102F
ister (SCDR)
See page 110.
Analog-to-Digital Control Status
$1030
Register (ADCTL)
See page 62.
Figure 2-7. Register and Control Bit Assignments (Sheet 4 of 6)
Freescale Semiconductor
Bit 7
6
5
Read:
TOF
RTIF
PAOVF
Write:
Reset:
0
0
0
Read:
DDRA7
PAEN
PAMOD
Write:
Reset:
0
0
0
Read:
Bit 7
Bit 6
Bit 5
Write:
Reset:
Indeterminate after reset
Read:
SPIE
SPE
DWOM
Write:
Reset:
0
0
0
Read:
SPIF
WCOL
Write:
Reset:
0
0
0
Read:
Bit 7
Bit 6
Bit 5
Write:
Reset:
Indeterminate after reset
Read:
(1)
TCLR
SCP2
SCP1
Write:
Reset:
0
0
0
Read:
R8
T8
Write:
Reset:
I
I
0
Read:
TIE
TCIE
RIE
Write:
Reset:
0
0
0
Read:
TDRE
TC
RDRF
Write:
Reset:
1
1
0
Read:
R7/T7
R6/T6
R5/T5
Write:
Reset:
Indeterminate after reset
Read:
CCF
SCAN
Write:
Reset:
0
0
= Unimplemented
I = Indeterminate after reset
M68HC11E Family Data Sheet, Rev. 5.1
Memory Map
4
3
2
1
PAIF
0
0
0
0
PEDGE
DDRA3
I4/O5
RTR1
0
0
0
0
Bit 4
Bit 3
Bit 2
Bit 1
MSTR
CPOL
CPHA
SPR1
0
0
1
U
MODF
0
0
0
0
Bit 4
Bit 3
Bit 2
Bit 1
SCP0
RCKB
SCR2
SCR1
0
0
U
U
M
WAKE
0
0
0
0
ILIE
TE
RE
RWU
0
0
0
0
IDLE
OR
NF
FE
0
0
0
0
R4/T4
R3/T3
R2/T2
R1/T1
MULT
CD
CC
CB
Indeterminate after reset
R
= Reserved
U = Unaffected
Bit 0
0
RTR0
0
Bit 0
SPR0
U
0
Bit 0
SCR0
U
0
SBK
0
0
R0/T0
CA
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