MC68HC711E20CFN2

Manufacturer Part NumberMC68HC711E20CFN2
DescriptionIC MCU 20K 2MHZ OTP 52-PLCC
ManufacturerFreescale Semiconductor
SeriesHC11
MC68HC711E20CFN2 datasheets
 

Specifications of MC68HC711E20CFN2

Core ProcessorHC11Core Size8-Bit
Speed2MHzConnectivitySCI, SPI
PeripheralsPOR, WDTNumber Of I /o38
Program Memory Size20KB (20K x 8)Program Memory TypeOTP
Eeprom Size512 x 8Ram Size768 x 8
Voltage - Supply (vcc/vdd)4.5 V ~ 5.5 VData ConvertersA/D 8x8b
Oscillator TypeInternalOperating Temperature-40°C ~ 85°C
Package / Case52-PLCCLead Free Status / RoHS StatusContains lead / RoHS non-compliant
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
Page 131
132
Page 132
133
Page 133
134
Page 134
135
Page 135
136
Page 136
137
Page 137
138
Page 138
139
Page 139
140
Page 140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
Page 137/242

Download datasheet (2Mb)Embed
PrevNext
9.4.5 Timer Counter Register
The 16-bit read-only TCNT register contains the prescaled value of the 16-bit timer. A full counter read
addresses the most significant byte (MSB) first. A read of this address causes the least significant byte
(LSB) to be latched into a buffer for the next CPU cycle so that a double-byte read returns the full 16-bit
state of the counter at the time of the MSB read cycle.
Register name: Timer Counter Register (High)
Bit 7
Read:
Bit 15
Write:
Reset:
0
Register name: Timer Counter Register (Low)
Bit 7
Read:
Bit 7
Write:
Reset:
0
= Unimplemented
Figure 9-15. Timer Counter Register (TCNT)
9.4.6 Timer Control Register 1
The bits of this register specify the action taken as a result of a successful OCx compare.
Address:
$1020
Bit 7
Read:
OM2
Write:
Reset:
0
Figure 9-16. Timer Control Register 1 (TCTL1)
OM[2:5] — Output Mode Bits
OL[2:5] — Output Level Bits
These control bit pairs are encoded to specify the action taken after a successful OCx compare. OC5
functions only if the I4/O5 bit in the PACTL register is clear. Refer to
Table 9-3. Timer Output Compare Actions
OMx
0
0
1
1
Freescale Semiconductor
Address: $100E
6
5
4
3
Bit 14
Bit 13
Bit 12
Bit 11
0
0
0
0
Address: $100F
6
5
4
3
Bit 6
Bit 5
Bit 4
Bit 3
0
0
0
0
6
5
4
3
OL2
OM3
OL3
OM4
0
0
0
0
OLx
Action Taken on Successful Compare
0
Timer disconnected from output pin logic
1
Toggle OCx output line
0
Clear OCx output line to 0
1
Set OCx output line to 1
M68HC11E Family Data Sheet, Rev. 5.1
Output Compare
2
1
Bit 0
Bit 10
Bit 9
Bit 8
0
0
0
2
1
Bit 0
Bit 2
Bit 1
Bit 0
0
0
0
2
1
Bit 0
OL4
OM5
OL5
0
0
0
Table 9-3
for the coding.
137