MC68HC711E20CFN2 Freescale Semiconductor, MC68HC711E20CFN2 Datasheet - Page 221

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MC68HC711E20CFN2

Manufacturer Part Number
MC68HC711E20CFN2
Description
IC MCU 20K 2MHZ OTP 52-PLCC
Manufacturer
Freescale Semiconductor
Series
HC11r
Datasheets

Specifications of MC68HC711E20CFN2

Core Processor
HC11
Core Size
8-Bit
Speed
2MHz
Connectivity
SCI, SPI
Peripherals
POR, WDT
Number Of I /o
38
Program Memory Size
20KB (20K x 8)
Program Memory Type
OTP
Eeprom Size
512 x 8
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
52-PLCC
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Bootloading a Program to Performa ROM Checksum
The bootloader ROM must be turned off before performing the checksum program. To remove the boot
ROM from the memory map, clear the RBOOT bit in the HPRIO register. This is normally a write-protected
bit that is 0, but in bootstrap mode it is reset to 1 and can be written. If the boot ROM is not disabled, the
checksum routine will read the contents of the boot ROM rather than the user’s mask ROM or EPROM at
the same addresses.
Inherent Delays Caused by Double Buffering of SCI Data
This problem is troublesome in cases where one MCU is bootloading to another MCU.
Because of transmitter double buffering, there may be one character in the serial shifter as a new
character is written into the transmit data register. In cases such as downloading in which this 2-character
pipeline is kept full, a 2-character time delay occurs between when a character is written to the transmit
data register and when that character finishes transmitting. A little more than one more character time
delay occurs between the target MCU receiving the character and echoing it back. If the master MCU
waits for the echo of each downloaded character before sending the next one, the download process
takes about twice as long as it would if transmission is treated as a separate process or if verify data is
ignored.
Boot ROM Variations
Different versions of the M68HC11 have different versions of the bootstrap ROM program.
summarizes the features of the boot ROMs in 16 members of the M68HC11 Family.
The boot ROMs for the MC68HC11F1, the MC68HC711K4, and the MC68HC11K4 allow additional
choices of baud rates for bootloader communications. For the three new baud rates, the first character
used to determine the baud rate is not $FF as it was in earlier M68HC11s. The intercharacter delay that
terminates the variable-length download is also different for these new baud rates.
synchronization characters, delay times, and baud rates as they relate to E-clock frequency.
Commented Boot ROM Listing
Listing 3. MC68HC711E9 Bootloader ROM
program in the MC68HC711E9 version of the M68HC11. Other versions can be found in Appendix B of
the M68HC11 Reference Manual.
Sync
Timeout
Character
Delay
$FF
4 characters
$FF
4 characters
$F0
4.9 characters
$FD
17.3 characters 5208
$FD
13 characters
Freescale Semiconductor
contains a complete commented listing of the boot ROM
Table 3. Bootloader Baud Rates
Baud Rates at E Clock =
2 MHz 2.1 MHz 3 MHz 3.15 MHz 4 MHz 4.2 MHz
7812
8192
11,718
12,288
1200
1260
1800
9600
10,080 14,400
15,120
5461
7812
3906
4096
5859
M68HC11 Bootstrap Mode, Rev. 1.1
Boot ROM Variations
Table 3
Table 3
shows the
15,624
16,838
1890
2400
2520
19,200
20,160
8192
10,416
10,922
6144
7812
8192
221

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