MC68030CRC33C Freescale Semiconductor, MC68030CRC33C Datasheet
MC68030CRC33C
Specifications of MC68030CRC33C
Related parts for MC68030CRC33C
MC68030CRC33C Summary of contents
Page 1
MC68030UM/AD ENHANCED 32-BIT MICROPROCESSOR USER'S MANUAL THIRD EDITION REV 2 ...
Page 2
Data Organization and Addressing Capabilities Coprocessor Interface Description Ordering Information and Mechanical Data Introduction Instruction Set Summary Processing States Signal Description On-Chip Cache Memories Bus Operation Exception Processing Memory Management Unit Instruction Execution Timing Applications Information Electrical Characteristics M68000 Family ...
Page 3
MOTOROLA ENHANCED 32-BIT MICROPROCESSOR USER'S MANUAL Motorola reserves the right to make changes further notice to any products herein reliability, function or design. Motorola ...
Page 4
MOTOROLA, INC. Published by Prentice-Hall, Inc. A Division of Simon & Schuster Englewood Cliffs, New Jersey 07632 The publisher offers discounts on this book when ordered in bulk quantities. For more information, write: Special Sales/College Marketing Prentice-Hall, Inc. ...
Page 5
TABLE OF CONTENTS Paragraph Number 1.1 Features. ................................................................................ 1.2 MC68030 Extensions to the M68000 Family ............................... 1.3 Programming Model ............................................................... 1-4 1.4 Data Types and Addressing Modes ........................................... 1.5 Instruction Set ................ ...
Page 6
TABLE OF CONTENTS (Continued) Paragraph Number 2,4. Indirect Preindexed Mode ..................................... 2-15 2,4,11 Program Counter Indirect with Displacement Mode .............. 2-16 2,4.12 Program Counter Indirect with Index (8-Bit Displacement) Mode ............................................................................ 2-16 2.4.13 Program ...
Page 7
TABLE OF CONTENTS (Continued) Paragraph Number 3.3.2 Conditional Tests .............................................................. 3-17 3.4 Instruction Set ......................................................... 3-18 3.5 Instruction Examples ............................................................... 3-25 3.5.1 Using the CAS and CAS2 Instructions ....................................... 3-25 3.5.2 Nested Subroutine ...
Page 8
TABLE OF CONTENTS (Continued) Paragraph Number 5.7.2 Cache Inhibit Output (CLOUT) ............................................. 5.7.3 Cache Burst Request (CBREQ) ............................................. 5.7.4 Cache Burst (CBACK). ..... .............................. 5.8 Interrupt Control Signals ......................................................... ...
Page 9
TABLE OF CONTENTS (Continued) Paragraph Number 6.3.1.2 Data Burst Enable ....................................................... 6.3.1.3 Clear Data Cache ....................................................... 6.3.1.4 Clear Entry in Data Cache ........................................... 6.3.1.5 Freeze Data Cache ..................................................... 6.3.1.6 Enable Data Cache ..................................................... 6.3.1.7 Instruction Burst Enable ............................................. 6.3.1.8 Clear ...
Page 10
TABLE OF CONTENTS (Continued) Paragraph Number 7.3.5 Synchronous Write 7.3.6 Synchronous Read-Modify-Write Cycle ............................... 7-54 7.3.7 Burst Operation Cycles ...................................................... 7-59 7.4 CPU Space Cycles ................................................................... 7-68 7.4.1 Interrupt Acknowledge Bus Cycles ...................................... 7-69 7.4.1.1 Interrupt Acknowledge Cycle 714.1.2 Autovector ...
Page 11
TABLE OF CONTENTS (Continued) Paragraph Number 8.1. Exceptions ........................................................... 8.1.13 Return Exception ....................................................... 8.2 Bus Fault Recovery ................................................................. 8.2.1 Special Status Word (SSW) .............. .................................. 8.2.2 Using Software ...
Page 12
TABLE OF CONTENTS (Continued) Paragraph Number 9.5.3.3 Table Sharing Tasks ...................................... 9.&3.4 Paging of Tables ........................................................ 9,&3 ...
Page 13
TABLE OF CONTENTS (Continued) Paragraph Number Coprocessor Interface Description 10.1 Introduction ........................................................................... 10.1.1 Interface Features .................................................. .......... 10-2 10.1.2 Concurrent Operation .......................................... 10.1.3 Coprocessor Instruction Format ......................................... 10.1.4 Coprocessor System Interface ........................................... 10.1.4.1 ...
Page 14
TABLE OF CONTENTS (Continued) Paragraph Number 10.2.3.4 Coprocessor Context Restore Instruction ....................... 10-27 10.2.3.4.1 Format ................................................................. 10-27 10.2.3.4.2 Protocol ............................................................... 10-28 10.3 Coprocessor Interface Register Set ........................................... 10-29 10.3.1 Response CIR ................................................................... 10-29 10.3.2 Control CIR ...................................................................... 10-30 10.3.3 Save ...
Page 15
TABLE OF CONTENTS (Continued) Paragraph 10.5,1.1 Coprocessor-Detected Protocol ..................... 10-62 10~5.1.2 Coprocessor-Detected Illegal ...
Page 16
TABLE OF CONTENTS (Continued) Paragraph Number 11.6 Instruction Tables ....................................................... 11.6.1 Fetch Effective Address (fea) ............................................. 11.6.2 Fetch Effective ...
Page 17
TABLE OF CONTENTS (Concluded) Paragraph Number 12.5.2 A 2-1-1-1 Burst Mode Bank Using .............. 12-24 12.5.3 A 3-1-1-1 Burst ...
Page 18
LIST OF ILLUSTRATIONS Figure Number 1-1 Block Diagram ..................................................................... 1-2 User Model .................................................... 1 ...
Page 19
LIST OF ILLUSTRATIONS (Continued) Figure Number 6-4 No-Write-Allocation and Write-Allocation Mode Examples ....... 6-5 Single Entry Mode Operation - - 8-Bit Port .............................. 6-6 Single Entry Mode Operation - - 16-Bit Port ............................. 6-7 Single Entry Mode Operation - - ...
Page 20
OF ILLUSTRATIONS (Continued) Figure Number 7-20 Asynchronous Byte Read Cycle Flowchart .............................. 7-21 Asynchronous Byte and Word Read Cycles - - 32-Bit Port ........ 7-22 Long-Word Read - - 8-Bit Port with CLOUT Asserted ................ ...
Page 21
LIST OF ILLUSTRATIONS (Continued) Figure Number 7-52 Long-Word Operand Late BERR on Third Access .... 7-53 Long-Word Operand BERR on Second Access ........ 7-54 ...
Page 22
LIST OF ILLUSTRATIONS (Continued) Figure Number 9-13 Long-Format Early Termination Page Descriptor ..................... 9-14 Long-Format Page Descriptor ................................................ 9-15 Short-Format Invalid Descriptor ............................................. 9-16 Long-Format Invalid Descriptor ............... .............................. 9-17 Short-Format Indirect Descriptor ........................................... 9-18 Long-Format Indirect Descriptor ............................. ....... ...
Page 23
LIST OF ILLUSTRATIONS (Continued) Figure Number 10-7 Coprocessor Interface Protocol for General Category Instructions ...................................................................... 10-8 Coprocessor nterface Protocol for Conditional Category Instructions ...................................................................... 10-9 Branch on Coprocessor Condition 10-10 Branch on Coprocessor Condition Instruction (cpBcc.L) ........... Set on Coprocessor ...
Page 24
LIST OF ILLUSTRATIONS (Continued) Figure Number 10-41 MC68030 Pre-lnstruction Stack Frame .................................... 10-57 10-42 Take Mid-Instruction Exception Primitive Format ..................... 10-58 10-43 MC68030 Mid-Instruction Stack Frame .............. . ............. :. ..... 10-59 10-44 Take Post-Instruction Exception Primitive Format 10-45 MC68030 ...
Page 25
LIST OF ILLUSTRATIONS (Concluded) Figure Number 12- ...
Page 26
Table Number 1-1 Addressing Modes ................................................................... 1-11 i-2 Instruction Set ........................................................................ 1-13 2-1 IS-I/ Indirection Encodings ................................... .... 2-22 2-2 Effective Addressing Mode Categories ...................................... 2-24 3-1 Data ...
Page 27
LIST OF TABLES (Continued) Table 7-7 Data Bus Write Enable Signals for Byte, Word, and Ports .................................................................................. 7-8 DSACK, BERR, and HALT Assertion Results ...................... ...
Page 28
PREFACE The MC68030 User's Manual describes the capabilities, operation, and pro- gramming of the MC68030 32-bit second-generation enhanced microproces- sor. The manual consists of the following sections and appendix, For detailed information on the MC68030 instruction set refer to M68000PM/AD, ...
Page 29
Sections 11, and Appendix A. Appli- cations programmers can find most of the information they need in Sections 11, 12, and Appendix A. From a ...
Page 30
SECTION 1 INTRODUCTION The MC68030 is a second-generation full 32-bit enhanced microprocessor from Motorola. The MC68030 is a member of the M68000 Family of devices that combines a central processing unit (CPU) core, a data cache, an instruc- tion cache, ...
Page 31
O~ O0 PHYSICAL or) ADDRESS m :xl BUS BUS vvRITE PENDING 0 BUS CONTROL r'- MIDBOSEQUENCER AND CONTBOt I CONTROL STORE ...
Page 32
FEATURES The features of the MC68030 microprocessor are: • Object Code Compatible with the MC68020 and Earlier M68000 Micro- processors • Complete 32-Bit Nonmultiplexed Address and Data Buses 16 32-Bit General-Purpose Data and Address Registers • • Two 32-Bit ...
Page 33
THE FAMILY In addition to the on-chip instruction cache present in the MC68020, the MC68030 ...
Page 34
Figure 1-2 shows the user programming model, consisting of 16 32-bit general-purpose registers and two control registers: • General-Purpose 32-Bit Registers (D0-D7, A0-A7) • 32-Bit Program Counter (PC) • 8-Bit Condition Code Register (CCR) The supervisor programming model consists of ...
Page 35
MC68030. Only supervisor code uses this feature, and user application programs remain affected. Registers D0-D7 are used as data registers for bit and bit field (1 to ...
Page 36
All of the 16 general-purpose registers (DO-D7, AO-A7) may be used as index registers. The program counter (PC) contains the address of the next instruction to be executed by ...
Page 37
The status register, SR, (see Figure 1-4) stores the processor status. It contains the condition codes that reflect the results of a previous operation and can be used for conditional instruction execution in a program. The condition codes are extend ...
Page 38
The cache control register (CACR) controls the on-chip instruction and data caches of the MC68030. The cache address register (CAAR) stores an address for cache control functions. The CPU root pointer (CRP) contains a pointer to the root of the ...
Page 39
DATA TYPES ADDRESSING Seven basic data types are supported: 1. Bits 2. Bit Fields (Fields of consecutive bits, 1-32 bits long) 3. BCD Digits (Packed: 2 digits byte, Unpacked: 1 digit/byte) ...
Page 40
Register Direct Data Register Direct Address Register Direct Register Indirect Address Register Indirect Address Register Indirect with Pes';r~crement Address Register Indirect with P~ececrement Address Register Indirect with D:splacement Register Indirect with Index Address Register Indirect with Incex tS-Bit Displacement) Address ...
Page 41
VIRTUAL CONCEPTS The full addressing range of the MC68030 is 4 Gbytes (4,294,967,296 bytes each of eight ...
Page 42
Mnemonic Description ABCD. Add Decimal with Extend ADD Add ADDA Add Address ADDI Add Immediate ADDQ Add Quick ADDX Add with Extend AND Logical AND ANDI Logical AND Immediate ASL, ASR Arithmetic Shift Left and Right Bcc Branch Conditionally BCHG ...
Page 43
Mnemonic Description cpBcc Branch Conditionally cpDBcc Test Coprocessor Condition, Decrement and Branch cpGEN Coprocessor General Instruction 1.6.2 Virtual Machine A typical use for a virtual machine system is the development of software, such as an operating system, for a new ...
Page 44
The MMU supports virtual memory systems by translating logical addresses to physical addresses using translation tables stored in memory. The ...
Page 45
Memory management assigns a physical base address to a logical page. The system software then transfers data between secondary storage and memory one or more pages ...
Page 46
SECTION 2 DATA ORGANIZATION AND ADDRESSING CAPABILITIES Most external references to memory by a microprocessor are either program references or data references; they either access instruction words or op- erands (data items) for an instruction. Program references are references to ...
Page 47
Coprocessors are designed to support special computation models that require very specific but widely varying data operand types and sizes. Hence, coprocessor instructions can specify operands of any size ...
Page 48
Bit (O~<Modulo ( < Byte High-Order Byte I 16-Bit W ...
Page 49
Each byte of the packed BCD format contains two digits; the least significant four bits contain the least significant digit. ...
Page 50
All operations to the status register and CCR are word-sized operations, but for all CCR operations, the upper byte is read as all zeros and is ignored when written, regardless of privilege level. The supervisor programming model (see ...
Page 51
Figure 2-2), but the most efficient data transfers occur when data is aligned on the same byte boundary as its operand size. However, instruction words must be aligned ...
Page 52
BYTE BYTE n- 1 ° i, ADDRESS ADDRESS oAT BYTE USER-DEFINED VALUE Figure 2-2. Memory Data Organization MOTOROLA BIT 7 0 BYTEo 4172, ...
Page 53
A bit field operand is specified by base address that selects one byte in memory bit field offset that indicates the leftmost (base) bit of the bit field in relation to the most significant bit of ...
Page 54
The effective address field may require additional information to fully specify the operand address. This additional information, called the effective address extension, is contained in an additional word or words and is considered part of the instruction. Refer to 2.5 ...
Page 55
Address Register Direct Mode In the address register direct mode, the operand is in the address register specified by the effective address register field. GENERATION: 2 ASSEMBLER SYNTAX: MODE: REGISTER: AOORESS REGISTER: NUMBER OF EXTENSION WORDS: 2.4.3 Address Register ...
Page 56
GENERATION: ASSEMBLER SYNTAX: MODE: REGISTER: ADDRESS REGISTER: OPERAND LENGTH ( 4): MEMORY ADDRESS: NUMBER OF EXTENSION WORDS: 2.4.5 Address Register Indirect with Predecrement Mode In the address register indirect with predecrement mode, the operand is in memory, and ...
Page 57
Address Register Indirect the address register indirect with displacement mode, the operand is in memory. The address of ...
Page 58
Register Indirect (Base This addressing mode ...
Page 59
Memory Indirect Postindexed Mode In this mode, the operand and its address are in memory. The processor calculates an intermediate indirect memory address using the base register (An) and base displacement (bd). The processor accesses a long word at ...
Page 60
Memory Indirect Preindexed Mode In this mode, the operand and its address are in memory. The processor calculates an intermediate indirect memory address using the base register (An), a base displacement (bd), and the index operand (Xn.SIZE * SCALE). ...
Page 61
Indirect this mode, the ...
Page 62
Program Counter Indirect with Index (Base Displacement) Mode This mode is similar to the address register indirect with index (base dis- placement) mode described in 2.4.8 Address Register Indirect with Index (Base Displacement) Mode, but the PC is used ...
Page 63
Program Counter Indirect Postindexed This mode is similar to the memory indirect postindexed mode described in 2.4.9 Memory Indirect Postindexed Mode, register. Both the operand and operand address are ...
Page 64
Program Counter Memory Indirect Preindexed Mode This mode is similar to the memory indirect preindexed mode described in 2.4.10 Memory Indirect Preindexed Mode, but the PC is used as the base register. Both the operand and operand address are ...
Page 65
Absolute Short Addressing Mode In this addressing mode, the operand is in memory, and the address of the operand is in the extension word. The 16-bit address is sign-extended to 32 bits before it is used. 7 ¸ GENERATION: ...
Page 66
Immediate Data In this addressing mode, the operand is in one or two extension words' Byte Operation Operand is in the low-order byte of the extension word Word Operation Operand is in the extension word Long-Word Operation The high-order ...
Page 67
EFFECTIVE ADDRESS ENCODING SUMMARY Most of the addressing modes use one of the three formats shown in Figure 2-4. The single effective address instruction is in the format of the instruction word. The encoding of the mode field of ...
Page 68
D/A REGISTER W/L 15 D/A REGISTER W/L Field Definition Instruction: Genera Register Number Register Extensions: Register Index Regfster Number D/A Index Register Type O=Dn 1 =An W/L Word/Long-Word ...
Page 69
Table 2-2 shows the categories to which each of the effective addressing modes belong. Address Modes 2 Register Data Address Register Direct Address Register Indirect Address Register Indirect with Postincrement Address Register Indirect with Predecrement Address Register Indirect Displacement with ...
Page 70
Several of the addressing techniques described in this section use data reg- isters and address registers interchangeably. While the MC68030 provides this capability, its performance has been optimized for addressing with ad- dress registers. The performance of a program that ...
Page 71
For both the MC68020 and the MC68030, the register indirect modes can be extended further. Since displacements can be 32 bits wide, they absolute addresses or the results of expressions that contain absolute ad- dresses. This allows the general register ...
Page 72
---------]~ RECORD OF 4 WORDS NOTE: Regardless of array structure, software increments index by the appropriate amount to point to next ...
Page 73
The outer displacement (od) available in the memory indirect modes is added to the pointer in memory. The syntax for these modes is ([bd,An],Xn,od) and ([bd,An,Xn],od). When the pointer is the address of a structure in memory and the outer ...
Page 74
The indirect, suppressed index register mode (see Figure 2-10) uses the con- tents of register index to the pointer located at the address specified by the displacement. The actual data item is at the address in the ...
Page 75
The postindexed indirect mode (see Figure 2-12) uses the contents index to the pointer list at the displacement. Register Xn is used as an index to the structure of data items located at the address specified ...
Page 76
The postindexed indirect mode with outer displacement (see Figure 2-14) uses the contents index to the pointer list at the displacement. Register Xn is used as an index to the structure of data structures at the ...
Page 77
It is useful to examine the derived addressing modes available to a pro- grammer (without regard to the MC68030 effective addressing mode actually encoded) because the programmer need not be concerned about these de- cisions. The assembler can choose the ...
Page 78
Any of the following modes: The addressing modes defined in programming terms, which are derivations of the addressing modes provided by the MC68030 architecture, are as fol- lows: Immediate Data - - #data: The data is a ...
Page 79
Indexing: (An,Rn) Register pointer An with variable index Rn. (disp,An,Rn) Register pointer with constant and variable index (or a base address 2 with a variable index). (addr,Rn) Absolute address with variable index. (addr,An,Rn) Absolute address with two variable indexes. Subscripting: ...
Page 80
Memory Pointer: {[preindexed]) Memory pointer directly to data operand. ([preindexed],disp) Memory pointer as base with displacement to data operand. ([postindexed],Rn) Memory pointer with variable index. ([postindexed],disp,Rn) Memory pointer with constant and variable index. ([postindexed],Rn*scale) Memory pointer subscripted. ([postindexed], disp, Rn*scale) ...
Page 81
Programs can be easily ...
Page 82
MC68000/IVIC68008/IVIC68010 Address Extension Word 0jA I ~EG,STER Data ...
Page 83
User ...
Page 84
In this case, after either a push or pull operation, register An points to the next available space on the stack. This is illustrated as 2.8.3 Queues The user can implement queues with the address register indirect ...
Page 85
To implement the queue as a circular buffer, the relevant address register should be checked and adjusted, if necessary, before performing the or "get" operation. The address register is adjusted by subtracting the buffer length (in bytes) from the register. ...
Page 86
SECTION 3 INSTRUCTION SET SUMMARY This section briefly describes the MC68030 instruction set. Refer to the MC68000 Programmer's Reference Manual, MC68000PM/AD, details on the MC68030 instruction set. The following paragraphs include descriptions of the instruction format and the operands used ...
Page 87
Besides the operation code, which specifies the function to be performed, an instruction defines the location of every operand for the function. Instruc- tions specify an operand location in one of three ways: 1. Register Specification - - A register ...
Page 88
The following notations are used in this section. In the operand syntax state- ments of the instruction definitions, the operand on the right is the destination operand. An--any address register, A7- any data register, D7-D0 Rn=any address or ...
Page 89
The MOVE instructions with their associated addressing modes are the basic means of transferring and storing addresses and data. MOVE instructions transfer byte, word, and long-word ...
Page 90
Table 3 summary of the integer and floating-point data movement operations. Table 3-1. Data Movement Operations Instruction Operand Syntax EXG Rn, Rn LEA : <ea>,An LINK < d > MOVE <ea>,<ea> MOVEA <ea>,An MOVEM ...
Page 91
Instruction ADD ADDA ADDI ADDQ ADDX 3 CLR CMP CMPA CMPI CMPM CMP2 DlVS/DIVU DlVSL/DIVUL EXT EXTB MULS/MULU NEG NEGX SUB SUBA SUBI SUBQ SUBX 3:2.3 Logical Instructions The logical operation instructions (AND, OR, EOR, and NOT) perform logical operations ...
Page 92
Instruction Operand Syntax AND (ea),Dn Dn,(ea) ANDI #<data>,<ea> EOR Dn,<data>,<ea> EORI #(data),(ea) NOT (ea) OR (ea),Dn Dn,(ea) ORI #(data),(ea) TST (ea) 3.2.4 Shift and Instructions The arithmetic shift instructions (ASR and ASL) and logical ...
Page 93
Instruction ASL ASR 3 LSL LSR RQL ROR ROXL ROXR SWAP 3.2.5 Bit Instructions Bit manipulation operations are accomplished using the following instruc- tions: bit test (BTST), bit ...
Page 94
Table 3-5. Bit Mani Instruction Operand Syntax BCHG Dn,<ea) #(data),(ea) BCLR Dn,{ea) #(data),{ea) BSET Dn,(ea~ #(data),(ea) BTST Dn,(ea) #(data),(ea Bit Field The MC68030 ...
Page 95
Binary-Coded Decimal Instructions Five instructions support operations on binary-coded decimal (BCD) num- bers ...
Page 96
Control Instructions A set of subroutine call and return instructions and conditiona and uncon- ditional branch instructions perform program control operations. The no operation instruction (NOP) may be used to force synchronization ...
Page 97
Control Instructions Privileged instructions, trapping instructions, and instructions that use or modify the condition code register (CCR) provide system control operations. Table 3-9 summarizes these instructions. The TRAPcc instruction uses the same conditional ...
Page 98
Unit Instructions The PFLUSH instructions flush the address translation caches (ATCs) and can optionally select only nonglobal entries for flushing. PTEST performs a ...
Page 99
The CCR portion of the SR contains five bits which indicate the results of many integer instructions. Program ...
Page 100
Code Most operations take a source operand and a destination operand, compute, and store the result in the destination ...
Page 101
Table 3-12. Condition Code Computations (Sheet Operations BTST, BCHG; BSET, BCLR BFTST, BFCHG, BFSET, BFCLR BFFFO BFINS ...
Page 102
Table 3-13 lists the condition names, encodings, and tests for the conditional branch and set instructions. The test associated with each condition is ...
Page 103
INSTRUCTION SET SUMMARY Table 3-14 provides a alphabetized listing of the MC68030 instruction set listed by opcode, operation, and syntax. Table 3-14 use notational conventions for the operands, the subfields and qualifiers, and the operations performed by the instructions. ...
Page 104
Notations for operations that have two operands, written <0Perand> <op> <operand>, where <op> is one of the following: shifted by, rotated by--The source operand is shifted or rotated by the Notation for single-operand operations: -<operand>--The operand is logically complemented <operand>sign-extended--The ...
Page 105
Table 3-14. Instruction Set Summary (Sheet Opcode ABCD Source10 + Destination Destination ADD Source + Destination $ Destination ADDA Source + Destination 0 Destination ADDI Immediate Data + Destination I) Destination 3 ADDQ ...
Page 106
Table 3-14. Instruction Set Summary (Sheet Opcode CAS CAS Destination - - Compare Operand i) cc; CAS2 if Z, Update Operand I) Destination else Destination 0 Compare Operand CAS2 Destination Compare 1 i cc; ...
Page 107
Table 3-14. Instruction Set Summary (Sheet Opcode EORI Source ~ CCR II. CCR to CCR EORI If supervisor state to SR the Source ® else TRAP EXG Rx il EXT Destination Sign-Extended ...
Page 108
Table 3,14. Instruction Set Summary Sheet Opcode MOVES if supervisor state then Rn j Destination [DFC] or Source ISFC else TRAP MULS Source x Destination I) Destination MULU Source x Destination l) Destination NBCD 0 ...
Page 109
Table 3-14. Instruction Set Summary (Sheet Opcode RTD (SP RTE If supervisor state the (SP) I) SR; SP+20 SP; (SP SP; ...
Page 110
INSTRUCTION EXAMPLES The following paragraphs provide examples of how to use selected instruc- tions. 3.5.1 Using the CAS and CAS2 Instructions The CAS instruction compares the value in a memory location with the value in a data register, and ...
Page 111
The CAS and CAS2 instructions together allow safe operations in the ma- nipulation of system linked lists. Controlling a single location, HEAD in the example, manages a last-in-first-out linked list (see Figure 3-2). If the list is empty, HEAD contains ...
Page 112
The next code (see Figure 3-3) fragment shows the use of a CAS2 instruction to delete an element from a linked list. The first LEA instruction loads the effective address of HEAD into A0. The MOVE instruction loads the address ...
Page 113
The CAS2 instruction can also be used to correctly maintain a first-in-first- out doubly linked list. A doubly linked list needs two controlled locations, LIST-PUT and LIST-GET, which contain pointers to the last element inserted in the list and the ...
Page 114
DINSERT LEA LIST PUT, AO LEA LIST_GET MOVE.L A2,D2 MOVE.L (AO),DO TST L DO DILOOP BED DIEMPTY MOVE.L DO,(NEXT, A2) CLR.L D1 MOVE.L DI,(LAST, A2) lEA (LAST, D0),AI CAS2.L DO:D I,D 2:D 2,(A 0):(A I) BNE DILDOP BRA ...
Page 115
OOELETE DOLOOP 3 OOEMPTY ODOONE BEFORE DELETING ENTRY: LISTPUT J AFTER DELETING ENTRY: 3.5.2 Nested Subroutine Calls The LINK instruction pushes an address onto the stack, saves the stack ad- dress at which the address is stored, and reserves an ...
Page 116
Bit Field Operations One data type provided by the MC68030 is the bit field, consisting of as many as 32 consecutive bits. A bit field is defined by an offset from an effective address and a width value. The ...
Page 117
Another widely used application for bit field instructions is bit-mapped graph- ics. Because byte boundaries are ignored in these areas of memory, the field definitions used with bit field instructions are very helpful. 3.5.4 Pipeline Synchronization with the NOP Instruction ...
Page 118
SECTION 4 PROCESSING STATES This section describes the processing states of the MC68030. It describes the functions of the bits in the supervisor portion of the status register and the actions taken by the processor in response to exception conditions. ...
Page 119
STOP instruction special type of normal processing state, one without bus cycles stopped, not halted.) 4.1 PRIVILEGE LEVELS The processor operates at one of two levels of privilege: ...
Page 120
The operating system sets the MSP for each task to point to a task-related area of supervisor data space. This separates task-related su- pervisor activity from asynchronous, I/O-related supervisor tasks that may ...
Page 121
The bus cycles for an instruction executed at the user privilege level are classified as user references, and the values of the function codes on FCO-FC2 specify user address spaces. The memory management unit of the processor, when it is ...
Page 122
The processor specifies a target address space for every bus cycle with the function code signals according to the type of access ...
Page 123
EXCEPTION PROCESSING An exception is defined as a special condition that pre-empts normal pro- cessing. Both internal and external conditions cause exceptions. External conditions that cause exceptions are interrupts from external devices, bus errors, coprocessor detected errors, and reset. ...
Page 124
Details of exception processing are provided in SECTION 8 EXCEP- TION PROCESSING, and Table 8-1 lists the exception vector assignments. 4.3.2 Exception Stack Frame Exception processing ...
Page 125
4 ...
Page 126
SECTION 5 SIGNAL DESCRIPTION This section contains brief descriptions of the input and output signals in their functional groups, as shown in Figure 5-1. Each signal is explained in a brief paragraph with reference to other sections that contain more ...
Page 127
...
Page 128
Table 5-1. Signal Index (Sheet Signal Name Data Transfer and Size Acknowledge Synchronous Termination Cache Inhibit In Cache Inhibit Out Cache Burst Request Cache Burst Acknowledge Interrupt Priority Level Interrupt Pending ...
Page 129
FUNCTION CODE SIGNALS (FC0-FC2) These three-state outputs identify the address space of the current bus cycle. Table 4-1 shows the relationship of the function code signals to the privilege levels and the address spaces. Refer to 4.2 ADDRESS SPACE ...
Page 130
BUS CONTROL SIGNALS The following signals control synchronous bus transfer operations for the MC68030. 5.6.10perand Cycle Start (OCS) This output signal indicates the beginning of the first external bus cycle for an instruction prefetch or a data operand transfer. ...
Page 131
Data Strobe (DS) 5.6.6 During a read cycle, this three-state output indicates that an external device should place valid data on the data bus. During a write cycle, the data strobe indicates that the MC68030 has placed valid data on ...
Page 132
CACHE The following signals relate to the on-chip caches. 5.7.1 Cache Inhibit Input (CIIN) This input signal prevents data from being loaded into the MC68030 ...
Page 133
INTERRUPT CONTROL SIGNALS The following signals are the interrupt control signals for the MC68030. 5.8.1 Interrupt Priority Level Signals These input signals provide an indication of an interrupt condition and the encoding of the interrupt level from a peripheral ...
Page 134
Bus Grant (BG) This output indicates that the MC68030 will release ownership of the bus master when the current processor bus cycle completes. Refer to 7,7.2 Grant for more information. 5.9.3 Bus Grant Acknowledge (BGACK) This input indicates that ...
Page 135
EMULATOR SUPPORT SIGNALS The following signals support emulation by providing a means for an em- ulator to disable the on-chip caches and memory management unit and by supplying internal status information to an emulator. Refer to SECTION 12 APPLICATIONS ...
Page 136
CLOCK (CLK) The clock signal is the clock input to the MC68030 TTL-compatible signal Refer to SECTION 12 APPLICATIONS INFORMATION for suggestions on clock generation. 5.13 POWER SUPPLY CONNECTIONS The MC68030 requires connection to a VCC ...
Page 137
Signal Function Function Codes Address 8us Data Bus Transfer Size Operand Cycle Start External Cycle Start Read/Write Read-Modify-Write Cycle Address Strobe 5 Data Strobe Data Buffer Enable Data Transfer and Size Acknowledge i Synchronous Termination Cache Inhibit In Cache Inhibit ...
Page 138
SECTION 6 ON-CHIP CACHE MEMORIES The MC68030 microprocessor includes a 256-byte on-chip instruction cache and a 256-byte on-chip data cache that are accessed by logical (virtual) ad- dresses. These caches improve performance by reducing external bus activity and increasing instruction ...
Page 139
PHYSICAL BUS CONTROLLER I_~ ~,~RO~O~ ~ CONTROLLER o --t BUS CONTROL 0 SIGNALS 0 01 MICROSEOUENCER AND CONTROL STROCT, ON ~1, CONTROL STORE CONTROL LOGIC EXECUTION ...
Page 140
Both on-chip caches are 256-byte direct-mapped caches, each organized as 16 lines. Each line consists ...
Page 141
An external access is defined as "cachable" for either the instruction or data cache when all the following conditions apply: • The cache is enabled with the appropriate bit in the CACR set. • The CDIS signal is negated. • ...
Page 142
TAG ...
Page 143
Refer to Figure 6-2 for the instruction cache organization. Address bits select one Of 16 lines and its asso- ciated tag. The comparator compares the address and function code bits ...
Page 144
I ~ IA..; ...
Page 145
WRITE ALLOCATION. for either of two types of allocation for data cache entries that miss on write cycles. The state of the write allocation (WA) bit in the cache control register specifies either no write allocation or write allocation ...
Page 146
In this case, the data in the cache no longer matches that in physical memory and is stale. Since the write-allocation mode updates the cache during write cycles, the data in the cache remains consistent with physical memory. Note that ...
Page 147
READ-MODIFY-WRITE ACCESSES. 6.1.2.2 cycle is always forced to miss in the data cache. However, if the system allows internal caching of read-modify-write cycle operands (CLOUT and CIIN both negated), the processor either uses the data read from memory to update ...
Page 148
When a cachable read cycle provides data with both CIIN and BERR negated, the MC68030 attempts to fill the cache entry. Figure 6-5 shows the organi- zation of a line of data in the caches. The notation b0, bl, b2, ...
Page 149
CYCLE SIZE 1 BYTE 2 WORD With a 32-bit port, the same operation is shown in Figure 6-7. Only one read cycle is required. All four bytes (including the requested byte) are latched 6 during the cycle. CYCLE SIZE BYTE ...
Page 150
Figure 6-8 shows a misaligned access of a long word at address $06 from 8-bit port requiring eight bus cycles to complete. Reading this long-word an operand requires eight read cycles, since accesses to all eight addresses return 8-bit port-size ...
Page 151
The next example, shown in Figure 6- read of a misaligned long-word operand from devices that return 16-bit DSACKx encodings. The processor accepts the first portion of the operand, the word from address $06, and requests a word ...
Page 152
CYCLE SIZE ADDRESS LONG WORD $06 LONG WORD $08 Figure 6-10. Single Entry Mode Operation Misaligned Long Word and 32-Bit DSACKx Port If all bytes of a long word are cachable, CIIN must be negated for all bus cycles ...
Page 153
The bus controller requests a burst mode fill operation by asserting the cache burst request signal (CBREQ). The responding device may sequentially supply one to four long words of cachable data may assert the cache inhibit input signal ...
Page 154
CYCLE 1 XFIRST ACCESS OF 8URST OPERATI REQUI R ED OPERAND OR PREFETCH / ~ BURST MODE REQUESTED AND BURST MODE BEGINS HERE ACKNOWLEDGED ~ Figure 6-11. Burst Operation Cycles and Burst Mode The bursting mechanism allows ...
Page 155
The MC68030 does not assert CBREQ during the first portion of a access if the remainder of the access does not correspond to the same cache line. Figure 6-13 shows an example in which the first portion of a misaligned ...
Page 156
The assertion of CIIN during the first cycle of a burst operation causes the data to be latched by the processor, and if the requested operand is aligned (the entire operand is latched in the first cycle), the data is ...
Page 157
On the initial access of a burst operation, a "retry" (indicated by the assertion of BERR and HAL causes the processor to retry the bus cycle and assert CBREQ again. However, signaling a retry with simultaneous BERR and ...
Page 158
WA DBE CD tED Write Allocate DBE = Data Burst Enabl Clear Data Cache CED = Clear Entry in Data Cache FD = Freeze Data ...
Page 159
FREEZE DATA CACHE. When the FD bit is set and a miss occurs during a read or write of the data cache, the indexed entry is not replaced. However, write cycles that hit in the data cache cause the ...
Page 160
FREEZE INSTRUCTION CACHE. struction cache. When the FI bit is set and a miss occurs in the instruction cache, the entry (or line) is not replaced. When the FI bit is cleared to zero, a miss in the instruction ...
Page 161
6 ...
Page 162
SECTION 7 BUS OPERATION This section provides a functional description of the bus, the signals that control it, and the bus cycles provided for data transfer operations, It also describes the error and halt conditions, bus arbitration, and the reset ...
Page 163
Control signals indicate the beginning of the cycle, the address space and the size of the transfer, and the type of cycle. The ...
Page 164
Figure 7-2. Asynchronous Input Sample Window A device with a 32-bit port size can also provide a synchronous mode transfer. In synchronous operation, input signals are externally synchronized to the processor clock, and the ...
Page 165
OCS is asserted only at the beginning of the first external bus cycle. With respect to OCS, an "operand" is any entity required by the execution unit, whether a program or data item. The function ...
Page 166
Data Bus 7.1.4 The data bus signals (D0-D31) comprise a bidirectional, nonmultiplexed par- allel bus that contains the data being transferred to or from the processor. A read or write operation may transfer 8, l & 24 bits ...
Page 167
For synchronous bus cycles, external devices assert the synchronous ter- mination signal (STERM) as part of the bus protocol. During a read cycle, the assertion of STERM causes the processor to latch the data. During a write cycle, it indicates ...
Page 168
DSACKx inputs. Refer to Table 7-1 for DSACKx encodings and assertion results. Table 7-1. DSACK Codes ...
Page 169
LONG WORD OPERAND Figure 7-4 shows the required organization of data ports on the MC68030 bus for 8-, 16-, and 32-bit devices. The four bytes shown in Figure 7-4 are connected through the internal data bus and data multiplexer to ...
Page 170
REGISTER I MULTIPLEXER . . . . . EXTERNAL __[ B31-D24 DATA BUS I ADDRESS xxxxxxxO ADDRESSES xxxxxxxO ...
Page 171
Table 7-4. Data Bus Requirements for Read Cycles Transfer Size Size SlZl SIZ0 Byte Word Byte ...
Page 172
Table 7-5. MC68030 Internal to External Data Bus Transfer Size ..... SIZ1 Byte Wor~ ~yte 'on, Word *Due to the current implementation, this byte is output but never used don NOTE: The OP tables ...
Page 173
C-X 7 D24-D31 D16-D23 Figure 7-6. Long-Word Operand Write Timing (16-Bit Data Port) 7- CLK A2A31 Z X A~---k AD SIZO " -- ...
Page 174
SIZ0_SIZI_A0_A1 =1010 to transfer the remaining 16 bits. SIZ0 and SIZ1 indicate that a word remains to be transferred; A0 and A1 indicate that the corresponds word to an offset of two from the base address. ...
Page 175
SO CLK ~ , A2-A31 A0 \ FC0-FC2 SIZ1 " ~ R/W ~ --k_../ oc--~ DSACK1 J DSACK0 D24031 ~ ...
Page 176
For maximum performance, data items should be aligned on their natural boundaries. All instruction words and extension words must reside on word boundaries. Attempting to prefetch an instruction word at an odd address ...
Page 177
CLK ~2-~, Z[; 'co-'~ Z X ~,~,-X ~,zo~ 7 o~c,, OSACKO D24-031 D16-D23 D8-015 00-07 Figure 7-10. Misaligned Long-Word Transfer to Word Port 7- ...
Page 178
LONG WORD OPERAND (REGISTER) I OPO OP1 DATA BUS D31 I WORD MEMORY MSR PR OP1 OP3 N1 Figure 7-11. Misaligned Cachable Long-Word Transfer from Word Port Example 15 WORD OPERAND I 0P2 I oP3 D31 DATA BUS I ...
Page 179
7- CLK A~A3 A1 °EC s,z, ...
Page 180
Figures 7-15 and 7-16 show an example of a long-word transfer to an odd address in long-word-organized memory. In this example, a long-word access is attempted beginning at the least significant byte of a long-word-organized memory. Only one byte can ...
Page 181
WORD OPERAND (REGISTER) 0 DATA BUS 031 I WORD MEMORY MSB Figure 7-14. Example of Misaligned Cachable Word Transfer from Word Bus 31 i OPO J D31 7 I, MSB Figure 7-15. Misaligned Long-Word Transfer to Long-Word Port Table ...
Page 182
SO CLK ZX A2-A31 ___ FCO-FC2 - 7 SIZ1 - 7 SIZO - k --k._J ECS --k_./ OCS OSACK~ ____//------'~ DSACKO ...
Page 183
OPO D31 I MSB Figure 7-17. Misaligned Cachable Long-Word Transfer from Long-Word Bus IN 7.2.4 Address, Size, and Data Bus Relationships The data transfer examples show how the MC68030 drives data onto or receives data from the correct byte sections ...
Page 184
Transfer SlZl SIZ0 Size Byte Word Byte Long Word The table shows that the MC68030 transfers the number ...
Page 185
MC68030 versus MC68020 Dynamic Bus Sizing The MC68030 supports the dynamic bus sizing mechanism of the MC68020 for asynchronous bus cycles (terminated with DSACKx) with two restrictions. First, for a cachable access within the boundaries of an aligned long ...
Page 186
SIZO SIZ1 R/W NOTE: These select lines can be combined with the address decode circuitry, or all can be generated within the same programmed array logic unit. Figure 7-18. Byte Data Select Generation for 16- and ...
Page 187
Interactions 7.2 The organization and requirements of the on-chip instruction and data caches affect the interpretation of the DSACKx and STERM signals. Since the MC68030 attempts to load all data operands and instructions that are ...
Page 188
Note that, if the bus controller is executing other cycles, these aborted cycles due to cache hits may not be seen externally. Also, OCS is asserted for the ...
Page 189
For asynchronous read cycles, the value of CIIN is internally latched on the rising edge of bus cycle state 4. Refer to 7.3.1 Asynchronous Read Cycle for more details on the states for asynchonous read cycles. During any bus cycle ...
Page 190
To assure proper operation in a synchronous system when BERR or BERR and HALT is asserted after DSACKx, BERR (and HALT) must meet the ap- propriate setup time (parameter #27A) prior to the falling clock edge one clock cycle after ...
Page 191
Although the synchronous input signals (STERM, CIIN, and CBACK) must be stable for the appropriate setup and hold times relative to every rising edge of the clock during which AS is asserted, the assertion or negation of CBACK and CIIN ...
Page 192
Each of the bus cycles is defined as a succession of states. These states apply to the bus operation and are different from the processor states described in SECTION 4 PROCESSING STATES. The clock cycles used in the descrip- tions ...
Page 193
PROCESSOR ADDRESS DEVICE 1) ASSERT ECS/OCS FOR ONE-HALF CLOCK 2) SET R/WTO READ 3) DRIVE ADDRESS ON AO-A31 4) DRIVE FUNCTION CODE ON FCO-FC2 5) DRIVE SIZE (SIZO-SIZ1) (FOUR BYTES) 6) CACHE INHIBIT OUT (CLOUT) BECOMES VALID 7) ASSERT ADDRESS ...
Page 194
SO S2 CLK A,---- --- O Z3( s, WORD s,z0 ---k ____ ...
Page 195
SO $2 CLK Ao--'~ F<°E< LONG WORD --- -----k--/ 0c---~ CLO UT k DSACK1 ___/ \ 016-D23 " ~ D8-D15 DO-D7 b BYTE READ ...
Page 196
SO 82 CLK ZX A2-A31 --k A1 --k AO FCO-FC2 ~ X SlZl LONG WORD SIZO oc-- 8SACKT D8ACKO J D8EN D24-D31 D16-D23 D8-D15 DO-D7 ~ wo,, RFAo 'ONG WO,D OPFR.ND ...
Page 197
State 1 One-half clock later in state 1 ($1), the processor asserts AS indicating that the address on the address bus is valid. The processor also asserts DS also during $1. In addition, the ECS (and OCS, if asserted) signal ...
Page 198
Asynchronous Write Cycle During a write cycle, the processor transfers data to memory or a peripheral device. Figure 7- flowchart of a write cycle operation for a long-word transfer. The following figures show the functional write cycle ...
Page 199
SO S2 CLK A,.~--_X A,-- k A0-~ 'co-'~' D( SlZ1 =--'~ LON6 WORD .,~ __ °c~-k__/ 7 ¸¸ °sAc ...
Page 200
SO $2 CLK __ " FC0oFC2 ~ X SIZ WORD SIZO R --k__/ DSACK1 DSACKO ...