MC68030CRC33C Freescale Semiconductor, MC68030CRC33C Datasheet - Page 222

• Manufacturer Part Number: MC68030CRC33C
• Description: IC MPU 32BIT ENHANCED 128-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68030CRC33C

• Processor Type: M680x0 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 128-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 33MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 128
• Package Type: PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

MOTOROLA
The simultaneous assertion of BERR and HALT during a bus cycle normally
or fourth cycle of a burst operation, this signal combination indicates a bus
error processing, refer to 7.5.1. Bus Errors.
for long-word requests with two wait states inserted in the first access and
one wait cycle inserted in the subsequent accesses. Figure 7-39 shows a burst
operation that fails to complete normally due to CBACK negating prema-
turely. Figure 7-40 shows a burst operation that is deferred because the entire
cycle, three long words are transferred even though CBACK is only asserted
for two clock periods.
The burst operation sequence begins with states S0-$3, which are very sim-
indicates that the cycle should be retried. However, during the second, third,
error condition, which aborts the burst operation. In addition, the processor
remains in the halted state until HALT is negated. For information about bus
Figure 7-37 is a flowchart of the burst operation. The following timing dia-
grams show various burst operations. Figure 7-38 shows burst operations
operand does not correspond to the same cache line. Figure 7-41 shows a
burst operation aborted by CIIN. Because CBACK corresponds to the
ilar to those states for a synchronous read cycle except that CBREQ is as-
serted. $4-$9 perform the final three reads for a complete burst operation.
State 0
State 1
The burst operation starts with SO. The processor drives ECS low, indicating
the beginning of an external cycle. When the cycle is the first cycle of a
cessor places a valid address on A0-A31 and valid function codes on
processor drives R/W high, indicating a read cycle, and drives DBEN in-
active to disable the data buffers. SIZ0-SIZ1 become valid, indicating the
or in the appropriate TTx register.
One-half clock later in $1, the processor asserts AS to indicate that the
address on the address bus is valid. The processor also asserts DS during
$1. CBREQ is also asserted, indicating that the MC68030 can perform a
addition, ECS (and OCS, if asserted) is negated during $1.
read operation, OCS is driven low at the same time. During SO, the pro-
FC0-FC2. The function codes select the address space for the cycle. The
number of operand bytes to be transferred. CLOUT also becomes valid,
indicating the state of the MMU CI bit in the address translation descriptor
burst operation into one of its caches and can read in four long words. In
MC68030 USER'S MANUAL
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