MC68030CRC33C Freescale Semiconductor, MC68030CRC33C Datasheet - Page 92

• Manufacturer Part Number: MC68030CRC33C
• Description: IC MPU 32BIT ENHANCED 128-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68030CRC33C

• Processor Type: M680x0 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 128-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 33MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 128
• Package Type: PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

M O T O R O L A
3.2.4 Shift and R o t a t e Instructions
The arithmetic shift instructions (ASR and ASL) and logical shift instructions
Table 3-4 is a summary of the shift and rotate operations,
and without the extend bit. All shift and rotate operations can be performed
on either registers or memory.
may be specified in the instruction operation word (to shift from 1-8 places)
or in a register (modulo 64 shift count).
sition only. The SWAP instruction exchanges the 16-bit halves of a register.
Performance of shift/rotate instructions is enhanced so that use of the ROR
and ROL instructions with a shift count of eight allows fast byte swapping.
(LSR and LSL) provide shift operations in both directions. The ROR, ROL,
ROXR, and ROXL instructions perform rotate (circular shift) operations, with
Register shift and rotate operations shift all operand sizes. The shift count
Memory shift and rotate operations shift word-length operands one bit po-
AND
ANDI
EOR
EORI
OR
ORI
TST
NOT
Instruction
Dn,<data>,<ea>
#<data>,<ea>
Operand Syntax
#(data),(ea)
#(data),(ea)
(ea),Dn
Dn,(ea)
(ea),Dn
Dn,(ea)
(ea)
(ea)
M C 6 8 0 3 0 U S E R ' S M A N U A L
Table 3-3. Loqical Operations
Operand Size
8. I~, 32
8, 15.32
8, 16, 32
8, 16.32
8, 16, 32
8, 16. 32
8, 16, 32
8, 16. 32
8, 16, 32
8, 16.32
source ,*, destination I destination
source ~) destination I) destination
immediate data 0 destination I destination
source V destination I destination
source - - 0 to set condition codes
immediate data .& destination I destination
immediate data V destination I destination
destination i destination
Operation
3-7
3