MC68030CRC33C Freescale Semiconductor, MC68030CRC33C Datasheet - Page 143

• Manufacturer Part Number: MC68030CRC33C
• Description: IC MPU 32BIT ENHANCED 128-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68030CRC33C

• Processor Type: M680x0 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 128-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 33MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 128
• Package Type: PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

6 . 1 . 2 D a t a C a c h e
6-6
function code bits FC0, FC1, and FC2 in addition to address bits A31-A8. The
treated independently. Figure 6-3 illustrates the organization of the data cache.
the selected tag with address bits A31-A8 and FC2 from the internal prefetch
when there is a tag match and the corresponding valid bit (selected by A3-A2)
When the address and function code bits do not match o r t h e requested entry
operation for the required instruction word and loads the cache entry, pro-
vided the entry is cachable. A burst mode operation may be requested to fill
corresponding l o n g word is not valid (but one or more of the other three
valid bits for that line are set) a single entry fill operation replaces the required
The data cache stores data references to any address space except CPU space
and accesses made with the MOVES instruction. Operation of the data cache
and cache filling operations. The tag of each line in the data cache contains
cache control circuitry selects the tag using bits A7-A4 and compares it to
the corresponding bits of the access address to determine if a tag match has
word in the cache to determine if an entry hit has occurred. Misaligned data
transfers may span two data cache entries. In this case, the processor checks
for a hit one entry at a time. Therefore, it is possible that a portion of the
access results in a hit and a portion results in a miss. The hit and miss are
The operation of the data cache differs for read and write cycles. A data read
corresponding to each long word). Refer to Figure 6-2 for the instruction
cache organization. Address bits A 7 - A 4 select one Of 16 lines and its asso-
ciated tag. The comparator compares the address and function code bits in
request to determine if the requested word is in the cache. A cache hit occurs
is set. On a cache hit, the word selected by address bit A1 is supplied to the
instruction pipe.
is not valid, a miss occurs. The bus controller initiates a long-word prefetch
an entire cache line. If the function code and address bits match and the
long word only, using a normal prefetch bus cycle or cycles (no burst).
(FC =$7), including those references made with PC relative addressing modes
is similar to that of the instruction cache, except for the address comparison
occurred. Address bits A3-A2 select the valid bit for the appropriate long
cycle operates exactly like an instruction cache read cycle; when a miss
occur s , an external cycle is initiated to obtain the operand from memory,
and the data is loaded into the cache if the access is cachable. In the case of
a misaligned operand that spans two cache entries, two long words are
required from memory. Burst mode operation may also be initiated to fill an
entire line of the data cache. Read accesses from the CPU address space and
address translation table search accesses are not stored in the data cache.
MC68030 USER'S MANUAL
MOTOROLA