MC68030CRC33C Freescale Semiconductor, MC68030CRC33C Datasheet - Page 450

• Manufacturer Part Number: MC68030CRC33C
• Description: IC MPU 32BIT ENHANCED 128-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68030CRC33C

• Processor Type: M680x0 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 128-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 33MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 128
• Package Type: PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

MOTOROLA
10.5.1.2 COPROCESSOR-DETECTED ILLEGAL COMMAND OR CONDITION
10.5.1.3 COPROCESSOR DATA-PROCESSING EXCEPTIONS.
scribed ensures that the coprocessor cannot halt the main processor.
The coprocessor can signal a protocol violation to the main processor with
the take mid-instruction exception primitive. To maintain consistency, the
vector number should be 13, as it is for a protocol violation detected by the
ception handler does not modify the stack frame, the MC68030 returns from
the exception handler and reads the response CIR.
WORDS.
ten to the command CIR or condition CIR that the coprocessor does not
frame, an RTE instruction causes the MC68030 to reinitiate the instruction
that took the exception. The coprocessor designer should ensure that the
All Motorola M68000 coprocessors signal illegal command and condition
words by returning the take pre-instruction exception primitive with the
to the internal operation of a coprocessor are classified as data-processing-
flow after exception processing. Refer to 10.4.18
tion Primitives, 10.4.19 Take Mid-Instruction Exception Primitive, and 10.4.20
Take Post-Instruction Exception Primitive.
assert DSACKx, the main processor waits for the assertion of that signal (or
some other bus termination signal) indefinitely. The protocol previously de-
main processor. When the main processor reads this primitive, it proceeds
as described in 10.4.19
coprocessor should return the take pre-instruction exception primitive in the
instruction exception as described in 10.4.18
Primitive. If the exception handler does not modify the main processor stack
state of the coprocessor is not irrecoverably altered by an illegal command
or condition exception if the system supports emulation of the unrecognized
command or condition word.
exception defined by M68000 microprocessors and should be signaled to the
an appropriate exception vector number. Which of these three primitives is
struction operation where the main processor should continue the program
recognize. If a value written to either of these registers is not valid, the
response CIR. When it receives this primitive, the main processor takes a pre-
F-line emulator exception vector number 11.
related exceptions. These exceptions are analogous to the divide-by-zero
main processor using one of the three take exception primitives containing
used to signal the exception is usually determined by the point in the in-
Illegal coprocessor command or condition words are values writ-
MC68030 USER'S MANUAL
Take Mid-Instruction Exception Primitive. If the ex-
Take Pre-lnstruction Exception
Take Pre-lnstruction Excep-
Exceptions related
10-63
1(