MC68030CRC33C Freescale Semiconductor, MC68030CRC33C Datasheet - Page 132

• Manufacturer Part Number: MC68030CRC33C
• Description: IC MPU 32BIT ENHANCED 128-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68030CRC33C

• Processor Type: M680x0 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 128-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 33MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 128
• Package Type: PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

5.7.1 Cache Inhibit Input (CIIN)
5.7.3 Cache Burst Request (CBREQ)
5.7.4 Cache Burst Acknowledge (CBACK)
MOTOROLA
5.7
5.7.2 Cache Inhibit Output (CLOUT)
CACHE C O N T R O L S I G N A L S
to 6.1 ON-CHIP CACHE ORGANIZATION AND OPERATION for information
The following signals relate to the on-chip caches.
This input signal prevents data from being loaded into the MC68030 instruc-
tion and data caches. It is a synchronous input signal and is interpreted on
a bus-cycle-by-bus-cycle basis. CIIhi is ignored during all write cycles. Refer
This three-state output signal reflects the state of the CI bit in the address
translation cache entry for the referenced logical address, indicating that an
external cache should ignore the bus transfer. When the referenced logical
address is within an area specified for transparent translation, the CI bit of
the appropriate transparent translation register controls the state of CLOUT.
about the address translation cache and transparent translation. Also, refer
to SECTION 6 ON-CHIP CACHE MEMORIES for the effect of CLOUT on the
This three-state output signal requests a burst mode operation to fill a line
to burst mode operations.
This input signal indicates that the accessed device can operate in the burst
cache. Refer to 7.3.7
operation.
on the relationship of CIIN to the on-chip caches.
Refer to SECTION 9 MEMORY MANAGEMENT UNIT for more information
internal caches.
in the instruction or data cache. Refer to 6.1.3 Cache Filling for filling infor-
mation and 7.3.7
mode and can supply at least one more long word for the instruction or data
Burst Operation Cycles
Burst Operation
MC68030 USER'S MANUAL
Cycles for information about burst mode
for bus cycle information pertaining
5-7
5