MC68030CRC33C Freescale Semiconductor, MC68030CRC33C Datasheet - Page 138

• Manufacturer Part Number: MC68030CRC33C
• Description: IC MPU 32BIT ENHANCED 128-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68030CRC33C

• Processor Type: M680x0 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 128-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 33MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 128
• Package Type: PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

SECTION 6
MOTOROLA
grading the performance of the MC68030. An increase in instruction through-
The MC68030 microprocessor includes a 256-byte on-chip instruction cache
the availability of the bus for use by external devices (in systems with more
than one bus master, such as a processor and a DMA device) without de-
external bus is eliminated. Additionally, instruction throughput increases when
As shown in Figure 6-1, the instruction cache and the data cache are con-
combined to provide the
the MMU validates the access on a write, the information is transferred from
the cache (on a read) or to the cache and the bus controller (on a write).
When a hit does not occur, the MMU translation of the address is used for
whether or not the required operand is located in one of the on-chip caches,
the address translation cache of the MMU performs logical-to-physical ad-
ON-CHIP CACHE MEMORIES
and a 256-byte on-chip data cache that are accessed by logical (virtual) ad-
dresses. These caches improve performance by reducing external bus activity
and increasing instruction throughput.
Reduced external bus activity increases overall performance by increasing
put results when instruction words and data required by a program are
available in the on-chip caches and the time required to access them on the
instruction words and data can be accessed simultaneously.
nected to separate on-chip address and data buses. The address buses are
(MMU). The MC68030 initiates an access to the appropriate cache for the
requested instruction or data operand at the same time that it initiates an
access for the translation of the logical address in the address translation
cache of the MMU. When a hit occurs in the instruction or data cache and
an external bus cycle to obtain the instruction or operand. Regardless of
dress translation in parallel with the cache lookup in case an external cycle
is required.
MC68030 USER'S MANUAL
logical
address to the memory management unit
6-1
6