MC68030CRC33C Freescale Semiconductor, MC68030CRC33C Datasheet - Page 235

• Manufacturer Part Number: MC68030CRC33C
• Description: IC MPU 32BIT ENHANCED 128-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68030CRC33C

• Processor Type: M680x0 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 128-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 33MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 128
• Package Type: PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

7
7-74
7.4.2 Breakpoint Acknowledge Cycle
7.4.3 Coprocessor Communication Cycles
7.4.1.3 SPURIOUS INTERRUPT CYCLE. When a device does not respond to an
executed after the breakpoint acknowledge cycle completes. The breakpoint
ternal hardware to provide an instruction word directly into the instruction
type field of zero and provides the breakpoint number specified by the in-
word available), the processor takes an illegal instruction exception. Figure
the timing for a breakpoint acknowledge cycle that returns an instruction
word. Figure 7-48 shows the timing for a breakpoint acknowledge cycle that
signals an exception.
The MC68030 coprocessor interface provides instruction-oriented commu-
communication required to support coprocessor opera~ions uses the MC68030
type field (A16-A19) for a coprocessor operation is $2. A13"A15 contain the
the MOVES ~ instruction. Refer to SECTION 10 COPROCESSOR INTERFACE
this case. If HALT is also asserted, the processor retries the cycle.
The breakpoint acknowledge cycle is generated by the execution of a break-
pipeline as the program executes. This cycle accesses the CPU space with a
struction on address lines A2-A4. If the external hardware terminates the
cycle with DSACKx or STERM, the data on the bus (an instruction word) is
inserted into the instruction pipe, replacing the breakpoint opcode, and is
instruction requires a word to be transferred so that if the first bus cycle
accesses an 8-bit port, a second cycle is required. If the external logic ter-
7-46 is a flowchart of the breakpoint acknowledge cycle. Figure 7-47 shows
CPU space with a type field of $2.
Coprocessor accesses use the MC68030 bus protocol except that the address
bus supplies access information rather than a 32-bit address. The CPU space
coprocessor identification number (CplD), and A0-A4 specify the coprocessor
correspond to MMU instructions and are not generated by the MC68030 as
a result of the coprocessor interface. These cycles can only be generated by
DESCRIPTION for further information.
rious interrupt vector number, 24, instead of the interrupt vector number in
point instruction (BKPT). The breakpoint acknowledge cycle allows the ex-
minates the breakpoint acknowledge cycle with BERR (i.e., no instruction
nication between the processor and as many as seven coprocessors. The bus
interface register to be accessed. Coprocessor accesses to a CplD of zero
interrupt acknowledge cycle with AVEC, STERM, or DSACKx, the external
logic typically returns BERR. The MC68030 automatically generates the spu-
MC68030 USER'S MANUAL
MOTOROLA