MC68030CRC33C Freescale Semiconductor, MC68030CRC33C Datasheet - Page 8

• Manufacturer Part Number: MC68030CRC33C
• Description: IC MPU 32BIT ENHANCED 128-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68030CRC33C

• Processor Type: M680x0 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 128-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 33MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 128
• Package Type: PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

Vi
Paragraph
Number
5.9.3
5.10.1
5.10.3
5.11.1
5.11.3
5.11.4
5.12
5.14
6.3.1.1
5.7.2
5.7.3
5.7.4
5.8
5.8.1
5.8.2
5.8.3
5.9
5.9.1
5.9.2
5.10
5.10.2
5.11
5.11.2
5.13
6.1
6.1.1
6.1.2
6.1.2.1
6.1.2.2
6.1.3
6.1.3.1
6.1.3.2
6.2
6.3
6.3.1
Signal S u m m a r y .....................................................................
Bus Exception Control Signals .................................................
E m u l a t o r S u p p o r t Signals ........................................................
Clock (CLK) ...................... .... ..................................................
Power S u p p l y Connections
On-Chip Cache
Cache Reset ...........................................................................
Cache Control .........................................................................
Interrupt Control Signals .........................................................
Bus A r b i t r a t i o n Control Signals ................................................
A u t o v e c t o r (AVEC) ............................................................
Cache Disable (CDIS) .........................................................
Cache Inhibit Output (CLOUT) .............................................
Cache Burst Request (CBREQ) .............................................
Cache Burst A c k n o w l e d g e (CBACK). ..... ..............................
Interrupt Priority Level Signals ...........................................
Bus Request (BR) ..............................................................
Bus Grant (BG) .................................................................
Bus Grant A c k n o w l e d g e (BGACK) .......................................
Reset (RESET) ..................................................................
Halt (HALT) ................................................ .......................
Bus Error (BERR) ..............................................................
M M U Disable (MMUDIS) ........ :. ............... ..........................
Pipeline Refill (REFILL) .......................................................
Internal M i c r o s e q u e n c e r Status (STATUS) ...........................
Instruction Cache ..............................................................
D a t a
Cache Filling ........................................ ............................
Cache Control Register ......................................................
TABLE OF CONTENTS (Continued)
Interrupt Pending (IPEND) ...................................................
Write A l l o c a t i o n ..........................................................
Write Allocate ............... ..............................................
Rea d-Mo dify-W rite Accesses ......................... ~.. :i .............
Single Entry M o d e ..................... : ................................
Burst M o d e Filling ......................................................
Cache .......................................................................
O r g a n i z a t i o n
On-Chip Cache Memories
MC68030 USER'S MANUAL
Section 6
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Title
and Operation ...............................
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