MC68030CRC33C Freescale Semiconductor, MC68030CRC33C Datasheet - Page 366

• Manufacturer Part Number: MC68030CRC33C
• Description: IC MPU 32BIT ENHANCED 128-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68030CRC33C

• Processor Type: M680x0 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 128-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 33MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 128
• Package Type: PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

MOTOROLA
9.9 DEFINING AND USING PAGE TABLES IN AN OPERATING SYSTEM
9.9.1 Root Pointer Registers
to operating system design, with many of the tradeoffs discussed.
An operating system can use the CPU root pointer (CRP) register alone or
top level address translation table(s). The choice depends on the complexity
when only the CRP register is used. When the index to the top level translation
table is the function code value (FCL in TC register is set), supervisor and
When the translation tables use the CRP and function code lookup, supervisor
tables to provide a common mapping for all supervisor references.
When the mapping of the supervisor address space is identical for all tasks,
the SRP can be used in conjunction with the CRP to provide a more simple
Many factors must be considered when determining how to use the MMU
in an operating system. The MC68030 provides the flexibility required to
optimize an operating system for many system implementations. The ex-
ample operating system described in the next section presents one approach
both the CRP and the supervisor root pointer (SRP) registers to point to the
of the memory layout for the system. When only the CRP is used, it must
point to a translation table that maps all supervisor and user references.
address tables, both methods can provide the same functionality, but each
and user accesses are separate, and each task can have different supervisor
and user mappings. Alternatively, the entries in the function code tables that
correspond to the supervisor spaces for each task can all point to the same
and efficient way to define the mapping. This technique suppresses the use
of the function code (unless the program and data spaces require distinct
when their execution is attempted in the supervise mode. If execution of a
the MC68030 takes a privilege violation exception. F-line instructions with a
However, the supervisor and user translation tables can be separate even
user tables are separate at all lower levels. With proper structuring of the
has its advantages.
mappings) and separates supervisor and user accesses at the root pointer
level of the translation tables. A single translation table maps all supervisor
CplD other than zero are executed as coprocessor instructions by the MC68030.
not support automatically cause F-line unimplemented instruction exceptions
unimplemented F-line instruction with CplD = 0 is attempted in the user mode,
MC68030 USER'S MANUAL
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