MC68030CRC33C Freescale Semiconductor, MC68030CRC33C Datasheet - Page 548

• Manufacturer Part Number: MC68030CRC33C
• Description: IC MPU 32BIT ENHANCED 128-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68030CRC33C

• Processor Type: M680x0 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 128-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 33MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 128
• Package Type: PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

MOTOROLA
The structure of this design is very similiar to the previous design and can
similarly be divided into three main sections:
The same PAL equations listed in Figure 12-10 are used with the exception
of the TERM signal. Figure 12-13 shows the equation for TERM, which is
TERM is simply an address decode signal in this design because both read
the PAL. The required SRAM data setup time on write cycles is ensured by
the clock that completes the MC68030 write operation.
The memory section in this design uses 25-ns SRAMs rather than the 35-ns
write operations complete after the MC68030 write bus cycle, both address
the 74F244 buffers in time to meet the specified data setup time to the
will all systems be able to afford the fast devices. Fortunately, several small
used by the two clock read and write design.
and write operations complete in two clock periods. The other signals gen-
erated by the PAL have already been discussed in the previous design and
are not repeated here. A latched version of AS is generated by a 74F74
D-type flip-flop and used to qualify the individual byte select signals from
keeping the write strobes (W) active to the SRAMs until the rising edge of
SRAMs used in the previous design. The faster SRAMs compensate for the
74F373 transparent latches used on the address lines. Since the memory
and data are latched and held valid to the SRAMs until the write strobes (W)
changes to this design could assist designers with different cost/performance
of the MC68030. For instance, if the clock frequency is below approximately
negate. During read operations, the transparent latches on the address lines
remain in the transparent mode, allowing the SRAMs to provide data through
MC68030.
Not all systems require the performance of 20-MHz two-clock bus cycles, nor
ratios. The simplest and most direct method is to reduce the clock frequency
18.1 MHz, the same control logic supports two-clock bus cycles with 45-ns
TERM = /A16 * /A17 * /A16 * A30 ;immediate TES-TER-Mfor both reads and writes
2. The actual memory section (SRAMs).
3. The buffer/latch section (address and data).
1. The byte select and address decode section (provided by the PAL).
Figure 12-13. Example PAL Equation for Two-Clock Read and Write
MC68030 USER'S MANUAL
Memory Bank
12-23
1 ;