MC68030CRC33C Freescale Semiconductor, MC68030CRC33C Datasheet - Page 38

• Manufacturer Part Number: MC68030CRC33C
• Description: IC MPU 32BIT ENHANCED 128-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68030CRC33C

• Processor Type: M680x0 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 128-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 33MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 128
• Package Type: PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

MOTOROLA
The CPU root pointer (CRP) contains a pointer to the root of the translation
tree for the currently executing task of the MC68030. This tree contains the
tree describing the supervisor's address space.
The translation control register (TC) consists of several fields that control
the translation table structure.
The transparent translation registers, TT0 and TT1, can each specify separate
to define the area of memory and type of access; either read, write, or both
types of memory access can be directly mapped. The transparent translation
feature allows rapid movement of large blocks of data in memory or I/O
The MMU status register (MMUSR) contains memory management status
translation tree for a particular logical address.
The cache control register (CACR) controls the on-chip instruction and data
caches of the MC68030. The cache address register (CAAR) stores an address
for cache control functions.
configured to provide a separate address space for supervisor routines, the
supervisor root pointer (SRP) contains a pointer to the root of the translation
address translation. These fields enable and disable address translation, en-
able and disable the use of SRP for the supervisor address space, and select
or ignore the function codes in translating addresses. Other fields define the
size of memory pages, the number of address bits used in translation, and
blocks of memory as directly accessible without address translation. Logical
addresses in these areas become the physical addresses for memory access.
Function codes and the eight most significant bits of the address can be used
space without disturbing the context of the on-chip address translation cache
or incurring delays associated with translation table Iookups. This feature is
mapping information for the task's address space. When the MC68030 is
useful to graphics, controller, and real-time applications.
information resulting from a search of the address translation cache or the
MC68030 USER'S MANUAL
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