MC68030CRC33C Freescale Semiconductor, MC68030CRC33C Datasheet - Page 191

• Manufacturer Part Number: MC68030CRC33C
• Description: IC MPU 32BIT ENHANCED 128-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68030CRC33C

• Processor Type: M680x0 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 128-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 33MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 128
• Package Type: PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

7
7-30
7.3 DATA TRANSFER CYCLES
following signals:
The STERM signal can be generated from the address bus and function code
value and does not need to be qualified with the AS signal. If STERM is
The assertion of CIIN is ignored when the appropriate cache is not enabled
or when cache inhibit out (CLOUT) is asserted. It is also ignored during write
cycles or translation table searches.
The transfer of data between the processor and other devices involves the
The address and data buses are both parallel nonmultiplexed buses. The bus
ous/synchronous bus uses a handshake protocol to insure correct movement
of the data. In all bus cycles, the bus master is responsible for de-skewing
all signals it issues at both the start and the end of the cycle. In addition, the
from the slave devices. The following paragraphs define read, write, and
Although the synchronous input signals (STERM, CIIN, and CBACK) must be
stable for the appropriate setup and hold times relative to every rising edge
of the clock during which AS is asserted, the assertion or negation of CBACK
and CIIN is internally latched on the rising edge of the clock for which STERM
asserted and no cycle is in progress (even if the cycle has begun, ECS is
asserted and then the cycle is aborted), STERM is ignored by the MC68030.
Similarly, CBACK can be asserted independently of the assertion of CBREQ.
If a cache burst is not requested, the assertion of CBACK is ignored.
master moves data on the bus by issuing control signals, and the asynchron-
bus master is responsible for de-skewing the acknowledge and data signals
read-modify-write cycle operations. An additional paragraph describes burst
mode transfers.
is asserted in a synchronous cycle.
• Address Bus A0-A31
• Data Bus D0-D31
• Control Signals
STERM and DSACKx should
cycle.
MC68030 USER'S MANUAL
n e v e r
N O T E
be asserted during the same bus
MOTOROLA