MC68030CRC33C Freescale Semiconductor, MC68030CRC33C Datasheet - Page 53

• Manufacturer Part Number: MC68030CRC33C
• Description: IC MPU 32BIT ENHANCED 128-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68030CRC33C

• Processor Type: M680x0 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 128-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 33MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 128
• Package Type: PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

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2.4 ADDRESSING MODES
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The addressing mode of an instruction can specify the value of an operand
for an operand that can use one of the numerous defined modes. The (ea)
field. The value in the mode field selects one or a set of addressing modes.
The register field specifies a register for the mode or a submode for modes
that do not use registers.
formats of these instructions include appropriate fields for operands that use
A bit field operand is specified by:
The most significant bit of the base byte is bit field offset 0, the least significant
and 32 bits.
dressing mode.
operation word. The effective address field specifies the addressing mode
designation is composed of two 3-bit fields: the mode field and the register
only one addressing mode.
bit of the base byte is bit field offset 7, and the least significant bit of the
previous byte in memory is bit offset - 1 . Bit field offsets may have values
in the range of -231 to 231 - 1 , and bit field widths may range between 1
(with an immediate operand), a register that contains the operand (with the
register direct addressing mode), or how the effective address of an operand
in memory is derived. An assembler syntax has been defined for each ad-
Figure 2-3 shows the general format of the single effective address instruction
Many instructions imply the addressing mode for one of the operands. The
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2. A bit field offset that indicates the leftmost (base) bit of the bit field in
3. A bit field width that determines how many bits to the right of the base
1. A base address that selects one byte in memory,
relation to the most significant bit of the base byte, and
bit are in the bit field.
Figure 2-3. Single Effective Address Instruction Operation Word
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13
X
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12
X
11
X
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MC68030 USER'S MANUAL
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9
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8
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7
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6
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5
MODE
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EFFECTIVE ADDRESS
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REGISTER
MOTOROLA
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0
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